AD5662ARJ-1 AD [Analog Devices], AD5662ARJ-1 Datasheet - Page 5
AD5662ARJ-1
Manufacturer Part Number
AD5662ARJ-1
Description
2.7 V to 5.5 V, 250 uA, Rail-to-Rail Output 16-Bit DAC D/A in a SOT-23
Manufacturer
AD [Analog Devices]
Datasheet
1.AD5662ARJ-1.pdf
(20 pages)
Preliminary Technical Data
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
V
Table 2.
Parameter
t
t
t
t
t
t
t
t
t
t
1
1
2
3
4
5
6
7
8
9
10
Maximum SCLK frequency is 30 MHz at V
1
DD
= 2.7 V to 5.5 V; all specifications T
SCLK
SYNC
V
50
13
13
0
5
4.5
0
50
13
0
DIN
DD
= 2.7 V to 3.6 V
t
8
t
10
DD
Limit at T
= 3.6 V to 5.5 V, and 20 MHz at V
DB2 3
MIN
t
4
to T
t
5
MIN
t
V
33
13
13
0
5
4.5
0
33
13
0
6
MAX
DD
, T
= 3.6 V to 5.5 V
, unless otherwise noted.
MAX
t
3
Figure 2. Serial Write Operation
t
1
Rev. PrA | Page 5 of 20
t
2
DD
= 2.7 V to 3.6 V.
DB0
DD
t
7
) and timed from a voltage level of (V
t
9
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to sclk fall ignore
SCLK falling edge to SYNC fall ignore
IL
+ V
IH
)/2. See Figure 2.
AD5662