ICM7211ALPL INTERSIL [Intersil Corporation], ICM7211ALPL Datasheet - Page 7

• Manufacturer Part Number: ICM7211ALPL
• Description: 4-Digit, LCD Display Driver
• Manufacturer: INTERSIL [Intersil Corporation]

Input Configurations and Output Codes
The ICM7211A accepts a four-bit true binary (i.e., positive
level = logical one) input at pins 27 thru 30, least significant
bit at pin 27 ascending to the most significant bit at pin 30. It
decodes the binary input into seven-segment alphanumeric
“Code B” output, i.e., 0-9, dash, E, H, L, P, blank. These
codes are shown explicitly in Table 1. It will correctly decode
true BCD to a seven-segment decimal output.
The ICM7211A is designed to accept multiplexed binary or
BCD input. These devices provide four separate digit lines
(least significant digit at pin 31 ascending to most significant
digit at pin 34), each of which when taken to a positive level
decodes and stores in the output latches of its respective digit
the character corresponding to the data at the input port, pins
27 through 30.
The ICM7211AM is intended to accept data from a data bus
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
TABLE 1. OUTPUT CODES
BlNARY
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ICM7212AM
ICM7211A
CODE B
BLANK
ICM7211A
7
under processor control.
In these devices, the four data input bits and the two-bit digit
address (DA1 pin 31, DA2 pin 32) are written into input buffer
latches when both chip select inputs (CS1 pin 33, CS2 pin
34) are taken low. On the rising edge of either chip select
input, the content of the data input latches is decoded and
stored in the output latches of the digit selected by the con-
tents of the digit address latches.
An address of 00 writes into D4, DA2 = 0, DA1 = 1 writes into
D3, DA2 = 1, DA1 = 0 writes into D2, and 11 writes into D1.
The timing relationships for inputting data are shown in
Figure 2, and the chip select pulse widths and data setup and
hold times are specified under Operating Characteristics.
FIGURE 6. SEGMENT ASSIGNMENT
e
f
d
g
a
c
b