LTC2393CLX-16 LINER [Linear Technology], LTC2393CLX-16 Datasheet - Page 5

• Manufacturer Part Number: LTC2393CLX-16
• Description: 16-Bit, 1Msps SAR ADC With 94dB SNR
• Manufacturer: LINER [Linear Technology]

TIMING CHARACTERISTICS
SYMBOL
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above
AVP , DVP or OVP , they will be clamped by internal diodes. This product can
handle input currents up to 100mA below ground or above AVP , DVP or
OVP without latchup.
Note 4: AVP = DVP = OVP = 5V, f
4.096V unless otherwise noted.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defi ned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
range, otherwise specifi cations are at T
SMPL
CONV
ACQ
4
5
6
7
8
9
10
r
11
12
13
14
15
16
17
18
, t
f
PARAMETER
Sampling Frequency
Conversion Time
Acquisition Time
CNVST Low Time
CNVST High Time
CNVST↓ to BUSY Delay
RESET Pulse Width
SCLK Period
SCLK High Time
SCLK Low Time
SCLK Rise and Fall Times
SDIN Setup Time
SDIN Hold Time
SDOUT Delay After SCLK↑
SDOUT Delay After CS↓
CS↓ to SCLK Setup Time
Data Valid to BUSY↓
Data Access Time after RD↓ or BYTESWAP↑
Bus Relinquish Time
SMPL
= 1MHz, external reference equal to
4V
A
4V
0.5V
= 25°C. (Note 4)
Figure 1. Voltage Levels for Timing Specifi cations
t
DELAY
The
0.5V
CONDITIONS
C
(Note 9)
(Note 10)
C
L
L
l
= 15pF
= 15pF
denotes the specifi cations which apply over the full operating temperature
4V
0.5V
t
DELAY
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code fl ickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Bipolar full-scale error is the worst-case of –FS or +FS
untrimmed deviation from ideal fi rst and last code transitions and includes
the effect of offset error.
Note 8: All specifi cations in dB are referred to a full-scale ±4.096V input
with a 4.096V reference voltage.
Note 9: t
2 • (t
80MHz for rising capture. t
Note 10: Guaranteed by design.
13
50%
+ t
13
SETUP
of 8ns maximum allows a shift clock frequency up to
t
WIDTH
) for falling edge capture with 50% duty cycle and up to
50%
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
SETUP
239316F01
is the set-up time of the receiving logic.
12.5
MIN
250
20
20
10
5
4
4
2
1
2
1
LTC2393-16
TYP
MAX
600
385
1.0
15
10
1
8
8
239316p
UNITS
Msps
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns