SY10E136 Micrel Semiconductor, SY10E136 Datasheet
SY10E136
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SY10E136 Summary of contents
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... This practice will minimize switching noise which can reduce the maximum count frequency of the device, or significantly reduce margins against other noise in the system. 1 SY10E136 SY100E136 output will pulse LOW for one clock cycle output facilitates the E136's use in OUT Rev ...
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... BLOCK DIAGRAM NOTE: 1. This diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay. BITS 2 – 4 E136 Universal Up/Down Counter Logic Diagram 2 SY10E136 SY100E136 – Q ...
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... SY10E136 SY100E136 C CL OUT OUT ...
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... SY10E136 SY100E136 Condition — — Condition — — — — — — — ...
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... OUT OUT D – 111110 111111 Figure 1. 24-bit Cascaded E136 Counter 5 Q – – CLK CLK MSB OUT OUT IN D – – 000000 000001 SY10E136 SY100E136 5 C OUT OUT 5 ...
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... Table 1. Preset Inputs Versus Divide Ratio SY10E136 SY100E136 rather than input ...
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... OUT OUT D0 – D5 Figure 5. 24-bit Programmable Divider Architecture 7 000010 000001 000000 Q – – CLK CLK 1 MSB OUT OUT IN D0 – – D5 SY10E136 SY100E136 LOAD S 1 OUT OUT ...
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... This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc (408) 914-7878 http://www.micrel.com FAX WEB © 2000 Micrel Incorporated 8 SY10E136 SY100E136 Rev. 03 ...