CY28410 Cypress Semiconductor, CY28410 Datasheet - Page 5

• Manufacturer Part Number: CY28410
• Description: Clock Generator for Intel Grantsdale Chipset
• Manufacturer: Cypress Semiconductor

Document #: 38-07593 Rev. *C
Byte 1: Control Register 1
Byte 2: Control Register 2
Byte 3: Control Register 3
Bit
Bit
Bit
5
4
3
2
1
0
7
6
7
6
5
4
3
2
1
0
7
6
5
4
3
2
@Pup
@Pup
@Pup
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
DOT_96T/C
CPU[T/C]1
CPU[T/C]0
Reserved
USB_48
CPUT/C
SRCT/C
PCIF0
Name
Name
PCIF2
PCIF1
Name
SRC7
SRC6
SRC5
SRC4
SRC3
SRC2
PCIF
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
REF
PCI
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF Output Enable
0 = Disabled, 1 = Enabled
Reserved
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Allow control of SRC[T/C]7 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]5 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Description
Description
Description
CY28410
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