MAX9125ESE Maxim, MAX9125ESE Datasheet
MAX9125ESE
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MAX9125ESE Summary of contents
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... Pin Compatible with DS90LV032A o Guaranteed 500Mbps Data Rate o 300ps Pulse Skew (max) o Conform to ANSI TIA/EIA-644 LVDS Standard o Single +3.3V Supply o Low 70µA Shutdown Supply Current o Fail-Safe Circuit PART MAX9125EUE MAX9125ESE MAX9126EUE MAX9126ESE Applications LVTTL/LVCMOS DATA INPUT Features Ordering Information TEMP. RANGE PIN-PACKAGE -40° ...
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... SO (derate 8.7mW/°C above +70°C)................696mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Differential Part-to-Part Skew (Note 8) Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency (Note 9) _______________________________________________________________________________________ Quad LVDS Line Receivers with Integrated Termination | | V = 0.1V to 1.0V, common-mode voltage ...
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... V , and Note 2: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. Note 3: AC parameters are guaranteed by design and characterization. Note 4: C includes scope probe and test jig capacitance. L Note the magnitude difference of differential propagation delays in a channel; t ...
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V = 200mV +1.2V DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE 2.6 2.5 t PHLD 2.4 2.3 t PLHD 2.2 0 0.5 1.0 1.5 2.0 COMMON-MODE VOLTAGE (V) PULSE SKEW ...
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Quad LVDS Line Receivers with Integrated Termination Table 1. Input/Output Function Table ENABLES EN L All other combinations of ENABLE inputs IN2 V - 0.3V CC IN_+ R IN1 R IN1 IN_- MAX9125 Figure 1. Inputs with ...
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Figure 2. Transition Time and Propagation Delay Test Circuit IN_- IN_ _+) IN_ IN NOTE OUT_ Figure 3. Transition Time and Propagation Delay Timing Diagram GENERATOR ...
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Quad LVDS Line Receivers with Integrated Termination EN WHEN 1.5V 1.5V EN WHEN EN = GND t PLZ OUTPUT WHEN V = -100mV ID t PHZ OUTPUT WHEN V = +100mV ID Figure 5. High-Z Delay ...
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Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to ...
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Quad LVDS Line Receivers with Integrated Termination Pin Configuration TOP VIEW IN1- 1 IN1+ 2 OUT1 3 MAX9125 ...
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Quad LVDS Line Receivers with ______________________________________________________________________________________ Integrated Termination Package Information 11 ...
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... Integrated Termination Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product ...