MM74HC240 Fairchild, MM74HC240 Datasheet
MM74HC240
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MM74HC240 Summary of contents
Page 1
... CMOS circuitry, i.e., high noise immunity and low power consumption. It has a fanout of 15 LS-TTL equivalent inputs. The MM74HC240 is an inverting buffer and has two active LOW enables (1G and 2G). Each enable independently controls 4 buffers. All inputs are protected from damage due to static dis- charge by diodes to V and ground ...
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... Logic Diagram www.fairchildsemi.com 2 ...
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... The worst case leakage cur Min Max Units 1000 ns 500 ns 400 125 Units Guaranteed Limits 1.5 1.5 V 3.15 3.15 V 4.2 4.2 V 0.5 0.5 V 1.35 1.35 V 1.8 1.8 V 1.9 1.9 V 4.4 4.4 V 5.9 5.9 V 3.84 3.7 V 5.34 5.2 V 0.1 0.1 V 0.1 0.1 V 0.1 0.1 V 0.33 0.4 V 0.33 0.4 V 1.0 1 160 A www.fairchildsemi.com ...
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... Maximum Input Capacitance IN C Maximum Output Capacitance OUT Note 5: C determines the no load dynamic power consumption www.fairchildsemi.com Conditions Typ Guaranteed Limit ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com ...
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... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...
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... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com ...
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... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. ...