MM74HCT240 Fairchild, MM74HCT240 Datasheet
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MM74HCT240
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MM74HCT240 Summary of contents
Page 1
... Pin Assignments for DIP, SOIC, SOP and TSSOP Top View MM74HCT240 © 1999 Fairchild Semiconductor Corporation The MM74HCT240 is an inverting buffer and the MM74HCT244 is a non-inverting buffer. Each device has two active low enables (1G and 2G), and each enable inde- pendently controls 4 buffers. ...
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... Truth Tables MM74HCT240 HIGH Level L LOW Level Z High Impedance Logic Diagrams MM74HCT240 www.fairchildsemi.com MM74HCT244 MM74HCT244 ...
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... A 0 0.1 6.0 mA, V 4.5V 0.2 0.26 CC 7.2 mA, V 5.5V 0.2 0. GND, 0. GND 0. GND 4 0.6 1.0 3 Min Max Units 4.5 5 500 125 C A Units Guaranteed Limits 2.0 2.0 V 0.8 0 0 3.84 3.7 V 4.84 4.7 V 0.1 0.1 V 0.33 0.4 V 0.33 0.4 V 0.5 1 160 A 1.3 1.5 mA www.fairchildsemi.com ...
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... Parameter Maximum Output PHL PLH Propagation Delay Maximum Output PZL PZH Enable Time Maximum Output PLZ PHZ Disable Time AC Electrical Characteristics MM74HCT240, MM74HCT244 V 5.0V 10 Symbol Parameter Maximum Output PHL PLH L Propagation Delay C 150 Maximum Output ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20B Package Number M20D 5 www.fairchildsemi.com ...
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... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC20 6 ...
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... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. ...