CDP6402C Harris Corporation, CDP6402C Datasheet
CDP6402C
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CDP6402C Summary of contents
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... C (when transmitting 5-bit code +85 C The CDP6402 and CDP6402C can be used in a wide range of applications including modems, printers, peripherals, video terminals, remote data acquisition systems, and serial data links for distributed processing systems. 10V/400K PKG. The CDP6402 and CDP6402C are functionally identical. ...
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... CONTROL CLS1 CLS2 CRL MR RRC RECEIVER TIMING AND DRR CONTROL STOP LOGIC SFD DR OE TBRE FE CDP6402, CDP6402C TBR8 (MSB) TRANSMITTER BUFFER REGISTER PARITY LOGIC TRANSMITTER REGISTER MULTIPLEXER CONTROL REGISTER MULTIPLEXER RECEIVER REGISTER PARITY LOGIC RECEIVER BUFFER REGISTER THREE STATE BUFFERS PE RBR8 (MSB) FIGURE 1 ...
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... Absolute Maximum Ratings DC Supply-Voltage Range CDP6402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +11V CDP6402C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0 Input Current, Any One Input Device Dissipation Per Output Transistor For T = Full Package-Temperature Range A (All Package Types 100mW Operating-Temperature Range ( Package Type D (SBDIP -55 Package Type E (PDIP -40 CAUTION: Stresses above those listed in “ ...
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... OUT NOTES Typical values are for and nominal Operating current is measured at 200kHz or V CDP1802A system operating at maximum speed of 3.2MHz). CDP6402, CDP6402C - + 10%, Except as noted (Continued CDP6402 V V (NOTE (V) ...
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... TO 2 CYCLES FIGURE 3. TRANSMITTER TIMING WAVEFORMS CDP6402, CDP6402C Receiver Operation Data is received in serial form at the RRl input. When no data is being received, RRI input must remain high. The data is clocked through the RRC. The clock rate is 16 times the data rate. Receiver timing is shown in Figure 4. ...
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... NOTE Don’t Care CDP6402, CDP6402C TABLE 1. CONTROL WORD FUNCTION EPE SBS DATA BITS ...
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... A low to high transition on TBRL requests data transfer to the transmitter register. If the transmitter register is busy, transfer is automatically delayed so that the two characters are transmitted end to end. 24 TRE A high level on TRANSMITTER REGISTER EMPTY indicates completed transmission of a character including stop bits. CDP6402, CDP6402C TABLE 2. FUNCTION PIN DEFINITION DESCRIPTION 5-80 ...
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... See Pin 37 - CLS2 39 EPE† When PI is low, a high level on EVEN PARITY ENABLE generates and checks even parity. A low level selects odd parity. 40 TRC The TRANSMITTER REGISTER CLOCK is 16X the transmit data rate. † See Table 1 (Control Word Function) CDP6402, CDP6402C DESCRIPTION 5-81 ...
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... Maximum limits of minimum characteristics are the values above which all devices function. CONTROL INPUT WORD TIMING CONTROL WORD INPUT CRL STATUS OUTPUT TIMING STATUS OUTPUTS t SFDH SFD RECEIVER REGISTER DISCONNECT TIMING R BUS 0 R BUS 7 t RRDH RRD CDP6402, CDP6402C - + 5 20ns CDP6402 ...
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... Clock to TRE NOTES: 1. All measurements are made at the 50% point of the transition except three-state measurements Typical values for and nominal Maximum limits of minimum characteristics are the values above which all devices function. CDP6402, CDP6402C - + 5 ...
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... The start bit may be completely asynchronous with the clock pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding register, the OE signal will come true.. CDP6402, CDP6402C TRANSMITTER BUFFER REGISTER LOADED ...
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... Clock to Framing Error NOTES: 1. All measurements are made at the 50% point of the transition except three-state measurements Typical values for and nominal Maximum limits of minimum characteristics are the values above which all devices function. CDP6402, CDP6402C - + 5 ...