PCF8563TS Philips Semiconductors, PCF8563TS Datasheet - Page 13

• Manufacturer Part Number: PCF8563TS
• Description: Real-time clock/calendar
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9397 750 04855
Product specification
Fig 5. POR override sequence.
handbook, full pagewidth
SDA
SCL
power up
8.9.1 Characteristics of the I
8.9.2 START and STOP conditions
8.9 Serial interface
8 ms
The serial interface of the PCF8563 is the I
I
and how to use it , order no. 9398 393 40011 or I
The I
modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor. Data transfer may
be initiated only when the bus is not busy.
The I
message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device
that controls the message is the ‘master’ and the devices which are controlled by the
master are the ‘slaves’.
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the start condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the
stop condition (P); see
width
2
Fig 6. I
Fig 7. START and STOP conditions on the I
C-bus specification, including applications, is given in the brochure: The I
SDA
SCL
SDA
SCL
2
2
C-bus is for bidirectional, two-line communication between different ICs or
C-bus system configuration is shown in
500 ns
TRANSMITTER /
2
RECEIVER
C-bus system configuration.
MASTER
START condition
S
2000 ns
Figure
16 April 1999
2
C-bus
RECEIVER
SLAVE
7.
TRANSMITTER /
RECEIVER
SLAVE
2
C-bus. A detailed description of the
2
C-bus.
Figure
2
C Peripherals Data Handbook IC12.
6. A device generating a
TRANSMITTER
override active
MASTER
Real-time clock/calendar
STOP condition
© Philips Electronics N.V. 1999. All rights reserved.
P
PCF8563
MGM664
TRANSMITTER /
RECEIVER
MASTER
MBC622
2
C-bus
SDA
SCL
MBA605
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