PCF8563TS Philips Semiconductors, PCF8563TS Datasheet - Page 14

• Manufacturer Part Number: PCF8563TS
• Description: Real-time clock/calendar
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9397 750 04855
Product specification
8.9.3 Bit transfer
8.9.4 Acknowledge
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as a control signal; see
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related
clock pulse.
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte. Also a master receiver must generate an acknowledge after
the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
width
dth
Fig 8.
Fig 9. Acknowledge on the I
BY TRANSMITTER
DATA OUTPUT
DATA OUTPUT
BY RECEIVER
SCL FROM
Bit transfer on the I
MASTER
SDA
SCL
condition
START
S
16 April 1999
2
C-bus.
2
C-bus.
data valid
data line
stable;
1
allowed
change
of data
2
Figure
not acknowledge
8.
Real-time clock/calendar
© Philips Electronics N.V. 1999. All rights reserved.
acknowledge
8
MBC621
PCF8563
acknowledgement
clock pulse for
9
MBC602
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