X1286 Intersil Corporation, X1286 Datasheet - Page 9
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X1286
Manufacturer Part Number
X1286
Description
Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
Manufacturer
Intersil Corporation
Datasheet
1.X1286.pdf
(26 pages)
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Figure 2. Recommended Crystal connection
POWER CONTROL OPERATION
The power control circuit accepts a V
input. The power control circuit powers the clock from
V
power the device from V
V
Figure 3. Power Control
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external
32.768kHz quartz crystal to maintain an accurate
internal representation of the 1/100 of a second, sec-
ond, minute, hour, day, date, month, and year. The
RTC has leap-year correction. The clock also corrects
for months having fewer than 31 days and has a bit
that controls 24 hour or AM/PM format. When the
X1286 powers up after the loss of both V
V
is written to the clock register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
REV 1.1 7/8/04
BACK
BACK
BACK
V
.
, the clock will not operate until at least one byte
BACK
when V
CC
Off
< V
BACK
V
CC
- 0.2V. It will switch back to
CC
X1
X2
Voltage
when V
CC
On
and a V
CC
exceeds
CC
In
www.intersil.com
BACK
and
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the SSEC register reset to “0” at the
next sub-second update after the stop bit is written.
The 1Hz frequency output from the PHZ/IRQ pin will
be reset to restart after the stop bit is written. The RTC
continues to update the time while an RTC register
write is in progress and the RTC continues to run dur-
ing any nonvolatile write sequences. A single byte may
be written to the RTC without affecting the other bytes.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC performance
will also be dependent upon temperature. The frequency
deviation of the crystal is a function of the turnover
temperature of the crystal from the crystal’s nominal
frequency. For example, a >20ppm frequency deviation
translates into an accuracy of >1 minute per month.
these parameters are available from the crystal
manufacturer. Intersil’s RTC family provides on-chip
crystal
capacitance to tune oscillator frequency from +116 ppm
to –37 ppm when using a 12.5 pF load crystal. For more
detail information see the Application section.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
compensation
networks
to
adjust
X1286
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