PCF8820U Philips Semiconductors, PCF8820U Datasheet - Page 24

• Manufacturer Part Number: PCF8820U
• Description: 67 x 101 Grey-scale/ECB colour dot matrix LCD driver
• Manufacturer: Philips Semiconductors

Philips Semiconductors
8.1.1
During power-down (bit PD = 1) all static currents are
switched off (no internal oscillator, no timing, no LCD
segment drive system) and all LCD outputs are internally
connected to V
To decrease the voltage at V
features can be used:
During power-down:
8.1.2
Partial screen mode allows data to be displayed of
DDRAM bank 0 to 1 on the first 8 rows or bank 14 to 15 on
the last 8 rows, depending on the status of
bits DP
If bit MY = 0, data is displayed either on rows 0 to 7 (first
8 rows) or on rows 56 to 63 (last 8 rows).
If bit MY = 1, data is displayed either on rows 66 to 59 (first
8 rows) or on rows 10 to 3 (last 8 rows).
The partial screen mode also allows V
to save power.
Frame frequency calibration is not allowed in the partial
screen mode.
2000 Dec 07
Select the direct drive mode by setting bit DM = 1
resulting in V
Select the non direct drive mode by setting bit DM = 0,
resulting in V
All LCD outputs at V
Oscillator is off
Intermediate bias voltage generator is off
High voltage generator is disabled; however, the status
of bit HVE is unchanged (see Table 8)
An external V
The I
DDRAM contents is not cleared; DDRAM data can be
written
Register settings remain unchanged
Temperature measurement is not possible.
67 101 Grey-scale/ECB colour dot matrix
LCD driver
2
2
C-bus is operational; commands can be executed
to DP
P
P
OWER
ARTIAL SCREEN MODE
0
SS
LCDOUT
LCDOUT
.
LCD
-
DOWN MODE
.
can be disconnected from V
SS
= V
= 0 V (output high-impedance).
(display off)
DD2
LCDOUT
very fast the following
LCDIN
to be reduced
LCDIN
24
8.1.3
Bits Y
Table 4 Y-address
8.1.4
Different LCD bias voltage settings are required at
different multiplex rates. The status of bits BS
bit BS
the intermediate bias voltage levels between
V
selected by bit BS
selected by bits BS
A value ‘n’ attributed to each bias system is used to
calculate these levels (see Table 5).
The optimum value for ‘n’ is given by:
M is the multiplex rate.
Table 6 shows how bias voltage levels are calculated for
three of the available bias systems using supported ‘n’
values.
LCDIN
Y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4
4
1
/
and V
to Y
2
Y
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Y-
B
select different ‘bias systems’ which determine
3
IAS SYSTEM
ADDRESS OF
0
define the Y-address of the DDRAM.
SS1
Y
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
2
. It should be noted that the bias system
1
/
2
2
Y
to BS
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
is independent of the bias systems
1
DDRAM
0
Y
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
.
0
bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
bank 8
bank 9
bank 10
bank 11
bank 12
bank 13
bank 14
bank 15
bank 16
Product specification
n
RAM BANK
=
PCF8820
M 3
2
to BS
–
where
0
and