PCF8820U Philips Semiconductors, PCF8820U Datasheet - Page 7

• Manufacturer Part Number: PCF8820U
• Description: 67 x 101 Grey-scale/ECB colour dot matrix LCD driver
• Manufacturer: Philips Semiconductors

Philips Semiconductors
6.2.12
These inputs (SA0 and SA1) allow up to four PCF8820
drivers to be controlled on the same I
and SA1 represent respectively bit 0 and bit 1 of the slave
address.
6.2.13
Pad OSC must be connected directly to V
on-chip oscillator is used. No external components are
required. It should be noted that any voltage drop of V
may affect the performance of the on-chip oscillator.
An external clock must be connected to input OSC.
6.2.14
A LOW-level on input RES initializes the chip.
6.2.15
The test pads (T1, T2, T3, T4, T5 and T6) must not be
accessible to the user.
Pads T1, T3 and T4 must be connected to V
must be connected to V
left open-circuit.
7
7.1
The on-chip oscillator provides the clock signal for the LCD
system. The clock mode is controlled via the I
interface. A clock signal must always be present, except in
the Power-down mode, to prevent the LCD entering a
DC state.
7.2
The I
commands sent via the I
I
control the bus communication.
7.3
RC low-pass filters are provided on inputs SDA_IN, SCL
and RES to enhance noise immunity in electrically
adverse environments.
2000 Dec 07
2
C-bus slave receiver/transmitter and therefore it cannot
67 101 Grey-scale/ECB colour dot matrix
LCD driver
FUNCTIONAL DESCRIPTION
2
C-bus interface controller receives and executes the
Oscillator
I
Input filters
2
C-bus interface controller
S
O
E
T
EST PADS
LAVE ADDRESS INPUTS
XTERNAL RESET INPUT
SCILLATOR SIGNAL INPUT
DD1
2
C-bus. The PCF8820 acts as an
, and pads T2 and T6 must be
2
C-bus. Inputs SA0
DD1
SS1
2
when the
C-bus
, pad T5
DD1
7
7.4
The PCF8820 contains a 67
which stores the display data. The RAM comprises
17 banks of 101 bytes (17
last bank is implemented. During RAM access, data is
transferred to the RAM via the I
7.5
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not affected by operations on the I
7.6
The address counter generates write addresses to the
DDRAM. During a write operation, display data is stored at
the addressed locations.
7.7
The display address counter generates read addresses to
the DDRAM. During a read operation, display data is read
out to the LCD.
7.8
The command decoder receives command words which
are followed by data byte(s) from the I
command decoder identifies the command words and
determines the destination for the data byte(s).
7.9
The LCD driver section has 101 outputs (C0 to C100)
which should be connected directly to the column drive
inputs of the LCD. The column driver signals are
generated in accordance with the multiplexed row signals
and with the data in the display data latch.
The programmed grey-scale levels are built-up in the LCD
over four frames (N1
Figs 3, 4 and 5.
7.10
The LCD driver section has 67 outputs (R0 to R66) which
should be connected directly to the row drive inputs of the
LCD. The row driver signals are generated in accordance
with the selected LCD drive mode.
Display Data RAM (DDRAM)
Timing generator
Address counter
Display address counter
Command decoder
Column driver outputs
Row driver outputs
1
, N1
2
, N1
101
101
3
2
C-bus interface controller.
and N1
8 bits). Not all of the
Product specification
2-bit static RAM,
2
C-bus. The
4
PCF8820
) as shown in
2
C-bus.