CS5101 Cherry Semiconductor Corporation, CS5101 Datasheet - Page 5

• Manufacturer Part Number: CS5101
• Description: Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters
• Manufacturer: Cherry Semiconductor Corporation

The CS5101 is designed to regulate voltages in multiple
output power supplies. Functionally, it is similar to a
magnetic amplifier, operating as a switch with a delayed
turn-on. It can be used with both single ended and dual
ended topologies.
The V
is compared to an internal reference voltage and the
amplified differential signal is fed through an inverting
amplifier into the buffer, BUF. The buffered signal is com-
pared at the PWM comparator with the ramp voltage
generated by capacitor C
exceeds the control voltage V
comparator goes high, latching its state through the
LATCH, the output stage transistor Q
external power switch, usually an N-FET, turns on.
The SYNC circuit is activated at time t
the voltage at the SYNC pin exceeds the threshold level
(2.5V) of the SYNC comparator. The external ramp capac-
itor C
source I (200µA). At time t
with the control voltage V
comparator goes high, turning on the output stage and
the external power switch. At the same time, the PWM
comparator is latched by the RS latch, LATCH.
Figure 1. Waveforms for CS5101. The number to the left of each curve
refers to a node on the Application Diagram.
Ground Level
(Gate doesn't go
V
SY
below Gnd)
V
V
SY
SY
Ð V
R
1
2
3
4
5
6
FB
+ V
+ V
V
V
OUT
is allowed to charge through the internal current
0V
0V
0V
0V
0V
SY
SY
D
C
voltage is monitored by the error amplifier EA. It
t
1
t
2
t
3
Theory of Operation
t
4
SYNC Function
t
1
R
. When the ramp voltage V
C
2
, the ramp voltage intersects
and the output of the PWM
V
C
OUT
, the output of the PWM
V
V
D
D
+ V
D
1
1
turns on, and the
(Figure 1) when
Circuit Description: continued
R
V
V
V
V
V
V
V
SY
C
RAMP
S
L1
G
,
DS
5
The logic state of the LATCH can be changed only when
both the voltage level of the trailing edge of the power
pulse at the SYNC pin is less than the threshold voltage of
the SYNC comparator (2.5V) and the RAMP voltage is
less than the threshold voltage of the RAMP comparator
(1.65V). On the negative going transition of the secondary
side pulse V
latch at time t
sistor Q
and the external power switch (an N-FET) is turned off.
The value of the ramp capacitor C
switching frequency of the regulator and the maximum
duty cycle of the secondary pulse V
If the RAMP pin is pulled externally to 0.3V or below, the
SSPR is disabled. Current drawn by the IC is reduced to
less than 100µA, and the IC is in SLEEP mode.
The voltage at the V
age lockout comparator with hysteresis. When V
below the UVL threshold, the 5V reference and all the cir-
cuitry running off of it is disabled. Under this condition
the supply current is reduced to less than 500µA.
The V
V
V
nal, which determines if V
tion with the ramp signal to disable the output, but only
after the current cycle has finished and the RS latch is reset.
Therefore this fault will not cause the output to turn off
during the middle of an on pulse, but rather will utilize
lossless turn-off. This feature protects the FET from over-
voltage stress. This is accomplished through gate G
driving transistor Q
An additional fault signal is derived from the REF _ OK
comparator. V
through gate G
OK threshold. As in the V
disables the output after the current cycle has been com-
pleted. The fault logic will operate normally only when
V
The drain pin, V
power switch and derives energy from it to keep the out-
put stage in an off state when V
imum specified voltage.
CC
REF
REF
_ OK comparator. When V
voltage is within the specification limits of REF _ OK.
- 0.7V, a fault signal is sent to gate G
CC
4
. C
supply voltage is further monitored by the
R
SY
Õs output goes low disabling the output stage,
3
, gate G
REF
. Capacitor C
1
D
when the V
is monitored so to disable the output
monitors the voltage on the drain of the
4
CC
DRAIN Function
FAULT Function
on.
RAMP Function
2
pin is monitored by the undervolt-
output goes high, resetting the
CC
CC
R
REF
_ OK fault, the REF _ OK fault
is absent, works in conjunc-
is discharged through tran-
CC
C
voltage falls below the
or V
R
is reduced below
SY
is based on the
.
CC
is below the min-
1
. This fault sig-
CC
1
by
falls