EPM2210 Altera Corporation, EPM2210 Datasheet - Page 14

• Manufacturer Part Number: EPM2210
• Description: (EPMxxxx) JTAG & In-System Programmability
• Manufacturer: Altera Corporation

Logic Elements
Figure 2–6. MAX II LE
2–8
MAX II Device Handbook, Volume 1
Reset (DEV_CLRn)
labpre/aload
labclkena1
labclkena2
Chip-Wide
labclk1
labclk2
labclr1
labclr2
data1
data2
data3
data4
addnsub
Asynchronous
Clock Enable
Clear/Preset/
Load Logic
Clock &
LAB Carry-In
Select
Carry-In1
Carry-In0
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. Each register has data, true asynchronous load data, clock,
clock enable, clear, and asynchronous load/preset inputs. Global signals,
general-purpose I/O pins, or any LE can drive the register’s clock and
clear control signals. Either general-purpose I/O pins or LEs can drive the
clock enable, preset, asynchronous load, and asynchronous data. The
asynchronous load data input comes from the data3 input of the LE. For
combinational functions, the LUT output bypasses the register and drives
directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and DirectLink
routing connections and one drives local interconnect resources. This
allows the LUT to drive one output while the register drives another
output. This register packing feature improves device utilization because
the device can use the register and the LUT for unrelated functions.
Another special packing mode allows the register output to feed back into
Look-Up
(LUT)
Table
Core Version a.b.c variable
Chain
Carry
Register chain
routing from
previous LE
Carry-Out0
Carry-Out1
LAB Carry-Out
Synchronous
LAB-wide
Synchronous
Load
Clear Logic
Load and
Synchronous
LAB-wide
Clear
Register Bypass
Packed
Register Select
ADATA
ENA
D
PRN/ALD
CLRN
Register
Feedback
Q
Programmable
Register
Altera Corporation
December 2004
LUT chain
routing to next LE
Row, column,
and DirectLink
routing
Row, column,
and DirectLink
routing
Local Routing
Register chain
output