EPM2210 Altera Corporation, EPM2210 Datasheet - Page 52

• Manufacturer Part Number: EPM2210
• Description: (EPMxxxx) JTAG & In-System Programmability
• Manufacturer: Altera Corporation

In System Programmability
3–6
MAX II Device Handbook, Volume 1
f
For more information, see the chapter on Using Jam STAPL for ISP via an
Embedded Processor.
Programming Sequence
During in-system programming, 1532 instructions, addresses, and data
are shifted into the MAX II device through the TDI input pin. Data is
shifted out through the TDO output pin and compared against the
expected data. Programming a pattern into the device requires the
following six ISP steps. A stand-alone verification of a programmed
pattern involves only stages 1, 2, 5, and 6. These steps are automatically
executed by third-party programmers, the Quartus
Jam STAPL and Jam Byte-Code Players.
1.
2.
3.
4.
5.
6.
Enter ISP – The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode.
Check ID – Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
Sector Erase – Erasing the device in-system involves shifting in the
instruction to erase the device and applying an erase pulse(s). The
erase pulse is automatically generated internally by waiting in the
run/test/idle state for the specified erase pulse time of 500 ms for
the CFM block and 500 ms for each sector of the UFM block.
Program – Programming the device in-system involves shifting in
the address, data, and program instruction and generating the
program pulse to program the flash cells. The program pulse is
automatically generated internally by waiting in the run/test/idle
state for the specified program pulse time of 75 µs. This process is
repeated for each address in the CFM and UFM block.
Verify – Verifying a MAX II device in-system involves shifting in
addresses, applying the verify instruction to generate the read
pulse, and shifting out the data for comparison. This process is
repeated for each CFM and UFM address.
Exit ISP – An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode.
Core Version a.b.c variable
®
II software, or the
Altera Corporation
December 2004