SAA7151 Philips Semiconductors, SAA7151 Datasheet - Page 38

• Manufacturer Part Number: SAA7151
• Description: Digital multistandard colour decoder with SCART interface DMSD2-SCART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Notes
1. an internal sign-bit D8 set to HIGH indicates that all values are always negative
2. H-PLL does not operate in this condition; the system clock frequency is set to a value fixed by the last update and is
April 1993
OEDY
“12”
OEDC
VNOI1, VNOI0
BFON
BOFL2 to BOFL0
Note: The bottom flutter gate is active at
- - - - - - - -
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
within 7.1 % of the nominal frequency.
- HPLL is locked
- HPLL in VTR mode
- the vertical noise limiter (VNL)
- gating is switched by
is in the VTR mode
BFON-bit = 1 (subaddress 12)
Enable Y signals on YUV-bus:
Enable UV signals on YUV-bus:
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Vertical noise reduction mode:
Bottom flutter compensation switching: 0 = off; 1 = on (controlled by BOFL-bit)
Bottom flutter compensation
The bottom flutter circuit is able to compensate for horizontal phase jump of up to 16 s.
Gate 2
0
1
0
1
BOFL2
0
0
1
1
BOFL1
0
0
1
1
Gate 1
0
0
1
1
BOFL0
0
1
0
1
HPLL function
normal
disabled
double speed
unused
0 = output high-impedance; 1 = output active
0 = output high-impedance; 1 = output active
38
VNOI1
0
0
1
1
start at line number
297 for PAL (247 for NTSC; active to end of field)
298 for PAL (248 for NTSC; active to end of field)
.
303 for PAL (253 for NTSC; active to end of field)
304 for PAL (254 for NTSC; active to end of field)
.
VNOI0
0
1
0
1
vertical
pulse
gate 2
gate 1
(dependent on FEIN)
(dependent on FEIN)
mode
normal
searching
free-running
bypassed
programmable by BOFL(2-0)
000
Product specification
111
SAA7151B