XC3030L Xilinx, XC3030L Datasheet - Page 10
XC3030L
Manufacturer Part Number
XC3030L
Description
Logic Cell Array Families
Manufacturer
Xilinx
Datasheet
1.XC3030L.pdf
(50 pages)
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Figure 8. XACT Development System Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot
pattern represents the available programmable interconnection points (PIPs).
Some of the interconnect PIPs are directional. This is indicated on the XACT design editor status line:
ND is a nondirectional interconnection.
D:H->V is a PIP that drives from a horizontal to a vertical line.
D:V->H is a PIP that drives from a vertical to a horizontal line.
D:C->T is a “T” PIP that drives from a cross of a T to the tail.
D:CW is a corner PIP that drives in the clockwise direction.
P0 indicates the PIP is non-conducting , P1 is on.
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