MC68HC58 Motorola, MC68HC58 Datasheet - Page 28

• Manufacturer Part Number: MC68HC58
• Description: Data Link Controller
• Manufacturer: Motorola

2.3 Bus Loading
2.4 DLC Clock Sources
2.4.1 Logic Clock
2.4.2 Host Interface Clock
2-12
MOTOROLA
The total load capacitance (C
J1850, must be between 2470 pF and 16544 pF. Likewise, the load resistance
(R
time constant (the product of R
It is recommended that in J1850 VPW systems with less than 26 nodes, one node
should have a load capacitance of 3200 to 3300 pF and a load resistance of 1.5 k ,
with all other nodes having the nominal load of 470 pF and 10.6 k , as outlined in SAE
STANDARD J1850 – CLASS B DATA COMMUNICATIONS NETWORK INTER-
FACE. This helps to minimize the differences in loading between small and large sys-
tems. When there are more than 26 nodes in a system, the large single load should
be replaced with a nominal load to avoid exceeding maximum capacitance and mini-
mum resistance specifications.
There are two types of clock signals associated with each DLC. The logic, or system
clock, provides a reference frequency for internal operations and SAE J1850 bus op-
eration. Host interface clocks provide timing for transfers between the DLC and the
host MCU.
The DLC can operate with an external oscillator reference connected between OSC1
and OSC2, or with an external clock source applied to OSC1 (OSC2 left floating). In-
ternal clock frequency is determined by the value of the configuration byte oscillator
divisor (OSCD) field. The DLC can be configured for divisor values of 1, 2, 3, or 4. Re-
gardless of external clock frequency, in order to operate properly, a DLC must be con-
figured so that its internal clock frequency is 2 MHz.
It is recommended that the DLC be clocked by a ceramic resonator. Ceramic resona-
tors stabilize much more rapidly than crystal references (typically, 100 times faster),
and are less expensive, although they may have looser frequency tolerance. The DLC
can be configured to operate with 2, 4, 6, or 8 MHz resonators.
The DLC can operate with external clock input frequencies of 2, 4, 6, or 8 MHz. Refer
to APPENDIX A ELECTRICAL CHARACTERISTICS for more information.
Host interface circuitry within each type of DLC is clocked by a source in the host MCU.
When operating in parallel mode, the DLC is clocked by an M6800 bus clock signal
(CLK). In serial mode, the DLC is clocked by an SPI serial clock signal.
Either of the interface clocks can have any frequency from dc to 4.2 MHz. Duty cycle
must be 50%
signal is asserted. Refer to SECTION 4 DATA LINK CONTROLLER OPERATION for
more information on host MCU clocking.
LOAD
) on the network must be between 315
5%. The clocks need only be active during the time that the DLC CS
SIGNAL AND PIN DESCRIPTIONS
LOAD
LOAD
) on the J1850 VPW network, as specified in SAE
and C
LOAD
) must not exceed 5.2 s.
and 1575 . In addition, the network
TECHNICAL DATA
MC68HC58