MC68HC58 Motorola, MC68HC58 Datasheet - Page 36

• Manufacturer Part Number: MC68HC58
• Description: Data Link Controller
• Manufacturer: Motorola

3.1.1 SOF — Start of Frame Symbol
3.1.2 Data — In Frame Data Bytes
3-2
MOTOROLA
Variable pulse width (VPW) modulation is an encoding technique in which each bit is
defined by the time between successive transitions, and by the level of the J1850 bus
between transitions.
The non-destructive contention protocol on the J1850 bus defines both active and pas-
sive symbols. Active and passive bits are used alternately. A symbol is active when
one or more transmitters drive the J1850 bus. A symbol is passive when no transmit-
ters are driving the J1850 bus (a logical wired-OR arrangement).
Each logic one or logic zero contains a single transition, and can be at either the active
or passive level and one of two lengths, either 64 s or 128 s (T
rate), depending upon the encoding of the previous bit. The SOF, EOD, EOF and IFS
symbols are always encoded at an assigned level and length. For an illustration of
VPW symbol timing, refer to Figure 3-3.
Each frame has a maximum length of 12 bytes, excluding the start of frame (SOF), end
of data (EOD), normalization bit (NB), and end of frame (EOF) symbols.
Each frame begins with an SOF symbol, an active symbol, and therefore each data
byte (including the CRC byte) begins with a passive bit, regardless of whether it is a
logic one or a logic zero.
All VPW bit lengths stated in the following descriptions are typical values at a 10.4
kbps bit rate.
All frames transmitted onto the J1850 bus must begin with an SOF symbol. This indi-
cates to any listeners on the J1850 bus the start of a new frame transmission. The
SOF symbol is not used in the cyclical redundancy check (CRC) calculation.
The SOF symbol is defined as a passive to active transition followed by an active pe-
riod 200 s in length. Refer to Figure 3-3 (C). This allows the data bytes which follow
the SOF symbol to begin with a passive bit, regardless of whether it is a logic one or
a logic zero.
The data bytes contained in the frame include the frame header bytes and any actual
data being transmitted to the receiving node. The DLC can be used to transmit frames
using any of the header formats outlined in the SAE J1850 document. Refer to the
SAE J1850 – CLASS B DATA COMMUNICATIONS NETWORK INTERFACE for
more information about J1850 header formats.
Each data byte is made up of a series of logic one and logic zero symbols. Frames
transmitted by the DLC onto the J1850 bus must contain at least one data byte, and
therefore can be as short as one data byte and one CRC byte. Each data byte in the
frame is eight bits in length, transmitted most significant bit (MSB) to least significant
bit (LSB).
J1850 FRAME FORMAT
NOM
at 10.4 kbps baud
TECHNICAL DATA
MC68HC58