PALCE20V8 Advanced Micro Devices, PALCE20V8 Datasheet

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PALCE20V8

Manufacturer Part Number
PALCE20V8
Description
EE CMOS 24-Pin Universal Programmable Array Logic
Manufacturer
Advanced Micro Devices
Datasheet

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PALCE20V8 Family
EE CMOS 24-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. Its macrocells provide a universal device
architecture. The PALCE20V8 is fully compatible with
the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
Device logic is automatically configured according to the
user’s design specification. A design is implemented
using any of a number of popular design software pack-
ages, allowing automatic creation of a programming file
based on Boolean or state equations. Design software
also verifies the design and can provide test vectors for
the finished device. Programming can be accomplished
on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
Publication# 16491
Issue Date: February 1996
BLOCK DIAGRAM
Pin and function compatible with all GAL
20V8/As
Electrically erasable CMOS technology pro-
vides reconfigurable logic and full testability
High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
Direct plug-in replacement for a wide range of
24-pin PAL devices
Programmable enable/disable control
Outputs individually programmable as
registered or combinatorial
FINAL
Rev. D
OE/I
11
Amendment /0
Input
Mux.
I
12
MACRO
MC
I/O
0
0
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25
MACRO
MC
I/O
1
1
MACRO
MC
I/O
2
Programmable AND Array
2
MACRO
MC
I/O
3
40 x 64
4
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased
electrically.
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be
programmed as registered or combinatorial with an
active-high or active-low output. The output configura-
tion is determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
10
MACRO
MC
Peripheral Component Interconnect (PCI)
compliant
Preloadable output registers for testability
Automatic register reset on power-up
Cost-effective 24-pin plastic SKINNYDIP and
28-pin PLCC packages
Extensive third-party software and programmer
support through FusionPLD partners
Fully tested for 100% programming and func-
tional yields and high reliability
Programmable output polarity
5-ns version utilizes a split leadframe for
improved performance
I/O
4
I
4
1
– I
10
MACRO
MC
I/O
5
5
MACRO
MC
I/O
6
6
MACRO
MC
I/O
7
7
Input
Mux.
I
13
Advanced
Devices
16491D-1
CLK/I
Micro
0
2-155

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PALCE20V8 Summary of contents

Page 1

... Programmable enable/disable control Outputs individually programmable as registered or combinatorial GENERAL DESCRIPTION The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. Its macrocells provide a universal device architecture. The PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series devices and most 24-pin combinatorial PAL devices ...

Page 2

... PIN DESIGNATIONS CLK = Clock GND = Ground I = Input I/O = Input/Output Connect OE = Output Enable V = Supply Voltage CC 2-156 PLCC/LCC PALCE20V8 Family 16491D-3 ...

Page 3

... Consult the /5 local AMD sales office to confirm availability of spe- cific valid combinations and to check on newly re- Blank, /4 leased combinations. /5 Blank, /4 PALCE20V8H-15/25, Q-20/25 (Ind) AMD PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 Second Revision (Same algorithm as /4) OPERATING CONDITIONS C = Commercial ( + Industrial (– ...

Page 4

... AMD FUNCTIONAL DESCRIPTION The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells (MC Each macrocell can be configured as a registered out- put, combinatorial output, combinatorial I/O, or dedi- cated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complemen- tary outputs to provide user-programmable input signal polarity ...

Page 5

... These configurations are summarized in table 1 and il- lustrated in figure 2. If the PALCE20V8 is configured as a combinatorial de- vice, the CLK and OE pins may be available as inputs to the array. If the device is configured with registers, the CLK and OE pins cannot be used as data inputs. Registered Output Configuration The control bit settings are SG0 = 0, SG1 = 1 and SL0 0 ...

Page 6

... Feedback is not available on pins 18 (21) and 19 (23) in the combinatorial output mode. 2. This macrocell configuration is not available on pins 18 (21) and 19 (23). 2-160 OE Note 1 Combinatorial Output Active High Figure 2. Macrocell Configurations PALCE20V8 Family CLK Registered Active High Combinatorial I/O Active High V CC Note 1 ...

Page 7

... In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Security Bit A security bit is provided on the PALCE20V8 as a deter- rent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback and verification of the programmed pattern by a device programmer, securing proprietary designs from com- petitors ...

Page 8

... SG0 PALCE20V8 Family SL0 7 SG1 SG0 SL0 ...

Page 9

... SG0 PALCE20V8 Family AMD CLK SL0 3 SG1 SG1 ...

Page 10

... (Note 0 Max (Note 3) OUT CC Outputs Open ( mA) OUT V = Max MHz CC and I (or I and OZL IH OZH PALCE20V8H-15/25 Q-15/25 (Com’l) ) Operating + +4. +5.25 V Min Max 2.0 0.8 10 –100 10 –100 –30 –150 ...

Page 11

... calculated value and is not guaranteed can be found using the following equation 1/f MAX (internal feedback) – Test Conditions MHz OUT Min 1/(tS + tCO) 45.5 1/(tWH + tWL) 62.5 PALCE20V8H-15/25 Q-15/25 (Com’l) AMD Typ = -15 -25 Max Min Max ...

Page 12

... Input rise and fall times 2 ns – typical. 2-176 Input or Feedback Clock PD Registered V T Output 16491D-7 Input V T Output t WL 16491D-9 t PXZ - Output Disable/Enable PALCE20V8 Family 16491D-8 Registered Output 0. 0.5V OL 16491D-10 Input to Output Disable/Enable ...

Page 13

... Permitted Does Not Apply Output C L Switching Test Circuit Commercial 200 5 pF PALCE20V8 Family OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL ...

Page 14

... By utilizing 50% of the device, a midpoint is defined for From this midpoint, a designer may scale the I CC graphs up or down to estimate the I CC requirements for a particular design. 2-178 Frequency (MHz) I vs. Frequency CC PALCE20V8 Family 20V8H-5 20V8H-7 20V8H-10 20V8H-15/25 20V8Q-10 20V8Q-15/25 50 16491D-13 ...

Page 15

... ENDURANCE CHARACTERISTICS The PALCE20V8 is manufactured using AMD’s ad- vanced electrically erasable process. This technology Endurance Characteristics Symbol Parameter t Min Pattern Data Retention Time DR N Min Reprogramming Cycles uses an EE cell to replace the fuse link used in bipolar parts result, the device can be erased and reprogrammed— ...

Page 16

... AMD POWER-UP RESET The PALCE20V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature pro- vides extra flexibility to the designer and is especially valuable in simplifying state machine initialization ...

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