LTC6802-1_1 LINER [Linear Technology], LTC6802-1_1 Datasheet

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... When multiple LTC6802-1 devices are connected in series they can operate simultaneously, permitting all cell voltages in the stack to be measured within 13ms. To minimize power, the LTC6802-1 offers a measure mode, which simply monitors each cell for overvoltage and un- dervoltage conditions. A standby mode is also provided. ...

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... For more information on lead free part marking, go to: For more information on tape and reel specifications, go to: 2 PIN CONFIGURATION + + – – 0. 0.3V PART MARKING PACKAGE DESCRIPTION LTC6802G-1 44-Lead Plastic SSOP http://www.linear.com/leadfree/ http://www.linear.com/tapeandreel/ TOP VIEW 1 CSBI CSBO 44 2 SDO SDOI 43 3 ...

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... Monitor Every 500ms (CDC = 6) Monitor Every 2s (CDC = 7) + Current into the V Pin When Idle All Serial Port Pins at Logic ‘1’ All Serial Port Pins at Logic ‘0’ This MODE Current is Added LTC6802-1 MIN TYP MAX UNITS l 1.5 mV/Bit l –0.5 0.5 mV –0.12 ...

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... LTC6802-1 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T SYMBOL PARAMETER Discharge Switch On-Resistance Temperature Range Thermal Shutdown Temperature Thermal Shutdown Hysteresis Voltage Mode Timing Specifications t Measurement Cycle Time CYCLE t SDI Valid to SCKI Rising Setup 1 t SDI Valid to SCKI Rising Hold ...

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... FREQUENCY (Hz) ADC DNL 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 INPUT (V) LTC6802-1 Measurement Gain Error Hysteresis 85°C TO 25° 4.5 5.0 –250 –200 –150 –100 –50 0 CHANGE IN GAIN ERROR (ppm) 68021 G02 ADC Normal Mode Rejection ...

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... LTC6802-1 TYPICAL PERFORMANCE CHARACTERISTICS Cell Input Bias Current During Conversion 2.70 CELL INPUT = 3.6V 2.65 2.60 2.55 2.50 2.45 2.40 2.35 –40 – 100 120 TEMPERATURE (°C) 68021 G10 Internal Die Temperature Measurement vs Ambient Temperature 43. –1 –2 –3 DEVICE IN STANDBY PRIOR TO MAKING DIE MEASUREMENTS – ...

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... CDC = 2 5 REG 68021 G19 13.20 13.15 13.10 13.05 13.00 6 CELLS DISCHARGING 12.95 1 CELL 12.90 DISCHARGING 12.85 12. 68021 G21 LTC6802-1 Internal Discharge Resistance vs Cell Voltage T = –45° 25° 85° 105° 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CELL VOLTAGE (V) 68021 G20 Cell Conversion Time –40 – ...

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... The V pin does not sink current. REG TOS (Pin 35): Top of Stack Input. Tie TOS to V the LTC6802-1 is the top device in a daisy chain. Tie TOS – when the LTC6802-1 is any other device in a daisy chain. When TOS is tied to V ...

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... V MODE Information section. SDI (Pin 42): Serial Data Input. The SDI pin interfaces to any logic gate (TTL levels must be driven by the SDOI pin of another LTC6802 tied to V MODE Information section. SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS ...

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... LTC6802-1 BLOCK DIAGRAM 5 C12 10k 6 S12 7 C11 10k 10k 10k – V 10Ω 30 DIE NC TEMP 10 Δ∑ A/D CONVERTER MUX REFERENCE EXTERNAL TEMP TEMP1 TEMP2 REF REGULATOR 34 V REG WATCHDOG 37 TIMER WDTB 3 SCKO 2 SDOI ...

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... Information section. Communication between the LTC6802-1 and a host pro- cessor is handled by a SPI compatible serial interface. As shown in Figure 1, the LTC6802-1’s can pass data up and down a stack of devices using simple diodes for isolation. This operation is described in Serial Port in the Applica- tions Information section. ...

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... Figure 1. 96-Cell Battery Stack, Daisy Chain Interface. This is a Simplified Schematic Showing the Basic Multi-IC Architecture 12 BATTERIES #25 TO #84 AND LTC6802-1 LTC6802-1 ICs # CSBO CSBI SDOI SDO SCKO SDI + V SCKI C12 V MODE S12 GPIO2 C11 ...

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... To detect an open connection with larger than 0.1μF capacitance still on the pin, one must repeat step (3) above a number of times before proceeding to step (4). The algorithm above determines if the CN pin is open based on measurements of the N+1 Cell. For example 12-cell system, the algorithm finds opens on pins C1 LTC6802-1 68021fa 13 ...

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... LTC6802-1 OPERATION through C11 by looking at the measurements of cells B2 through B12. Therefore the algorithm cannot be used to determine if the topmost C pin is open. Fortunately, an open wire from the battery to the top C pin usually means the V pin is also floating. When this happens, the readings for the top battery cell will always be 0V, indicating a failure ...

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... An external resistor should be used to limit the power dissipated by the MOSFETs. The maximum power dissipation in the MOSFETs is limited by the amount of heat that can be tolerated by the LTC6802-1. Excessive heat results in elevated die temperatures. The electrical characteristics are guaranteed for die tempera- tures up to 85° ...

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... LTC6802-1 APPLICATIONS INFORMATION USING THE LTC6802-1 WITH LESS THAN 12 CELLS The LTC6802-1 can typically be used with as few as four cells. The minimum number of cells is governed by the supply voltage requirements of the LTC6802-1. The sum of the cell voltages must be 10V to guarantee that all electrical specifications are met. ...

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... UV and OV conditions at the rate designated by the CDC bits. Monitor Mode The LTC6802-1 can be used as a simple monitoring circuit with no serial interface by pulling the MMB pin low. When in this mode, the interrupt status is indicated on the SDO pin using the toggle polling mode described in the Serial Port section ...

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... C9 V REG S9 V REF C8 V TEMP2 S8 V TEMP1 C7 NC − LTC6802 CSBO CSBI SDOI SDO SCKO SDI + V SCKI C12 V MODE S12 GPIO2 C11 GPIO1 S11 WDTB C10 MMB S10 TOS C9 V REG S9 V REF ...

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... Physical Layer On the LTC6802-1, seven pins comprise the low side and high side ports. The low side pins are CSBI, SCKI, SDI, and SDO. The high side pins are CSBO, SCKO and SDOI. ...

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... The other devices in the stack must have TOS tied low. See Figure 1. Data Link Layer Clock Phase And Polarity: The LTC6802-1 SPI-compat- ible interface is configured to operate in a system using CPHA=1 and CPOL=1. Consequently, data on SDI must be stable during the rising edge of SCKI. ...

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... The master pulls CSBI high to exit polling. Level polling: Level polling is enabled when the LVLPL bit is high. After entering a polling command, the data out line will be driven by the slave devices based on their status. When polling for the A/D converter status, data LTC6802-1 68021 F10 68021fa 21 ...

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... LTC6802-1 APPLICATIONS INFORMATION out will be low when any device is busy performing an A/D conversion and will be high when no device is busy. Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will be high when none has an interrupt condition. ...

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... CELL10 bit=0) 0x7C (cell 12 only, if CELL10 bit=0) 0x7D (unused) 0x7E (cell self test 1; all CV=0x555) 0x7F (cell self test 2; all CV=0xAAA) LTC6802-1 68021fa 23 ...

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... LTC6802-1 APPLICATIONS INFORMATION Memory Map Table 7 through Table 12 show the memory map for the LTC6802-1. Table 12 gives bit descriptions. Table 7. Configuration (CFG) Register Group REGISTER RD/WR BIT 7 CFGR0 RD/WR WDT CFGR1 RD/WR DCC8 CFGR2 RD/WR MC4I CFGR3 RD/WR MC12I CFGR4 RD/WR VUV[7] CFGR5 RD/WR VOV[7] Table 8. Cell Voltage (CV) Register Group ...

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... ETMP1[6] ETMP1[5] ETMP1[4] ETMP2[2] ETMP2[1] ETMP2[0] ETMP2[9] ETMP2[8] ITMP[6] ITMP[5] ITMP[4] REV[1] REV[0] THSD BIT 6 BIT 5 BIT 4 PEC[6] PEC[5] PEC[4] LTC6802-1 BIT 3 BIT 2 BIT 1 C2OV C2UV C1OV C6OV C6UV C5OV C10OV C10UV C9OV BIT 3 BIT 2 BIT 1 ETMP1[3] ETMP1[2] ETMP1[1] ETMP1[11] ETMP1[10] ...

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... LTC6802-1 APPLICATIONS INFORMATION Table 12. Memory Bit Descriptions NAME DESCRIPTION CDC Comparator Duty Cycle CELL10 10-Cell Mode LVLPL Level Polling Mode GPIO1 GPIO1 Pin Control GPIO2 GPIO2 Pin Control WDT Watchdog Timer DCCx Discharge Cell x VUV Undervoltage Comparison Voltage* VOV Overvoltage Comparison Voltage* ...

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... APPLICATIONS INFORMATION SERIAL COMMAND EXAMPLES LTC6802-1 (Daisy Chained Configuration) Examples below use a configuration of three stacked devices: bottom (B), middle (M), and top (T) Write Configuration Registers 1. Pull CSBI low 2. Send WRCFG command byte 3. Send CFGR0 byte for top device, then CFGR1 (T), CFGR2 (T), … CFGR5 (T) 4. Send CFGR0 byte for middle device, then CFGR1 (M), CFGR2 (M), … ...

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... Clamp diodes at each pin to V & V alternate power-path if there are other devices (which can supply power) connected to the LTC6802-1. Diode conduction at data ports will impair communication with higher-potential units. All units above the disconnection will enter standby mode within 2 seconds of disconnect. Discharge switches are disabled in standby mode ...

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... The FMEA scenarios that are potentially most damaging are those that involve a break in the stack of battery cells. When the battery stack has a discontinuity between groupings of cells monitored by LTC6802-1 ICs, any load will force a large reverse potential on the daisy-chain connection. This situation might occur in a modular battery system during initial installation or a service procedure ...

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... A decoupling network of 20Ω /100nF is recommended. READING EXTERNAL TEMPERATURE PROBES Using Dedicated Inputs The LTC6802-1 includes two channels of ADC input, V and V , that are intended to monitor thermistors TEMP2 (tempco about –4%/°C generally) or diodes (–2.2mV/°C typical) located within the cell array ...

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... APPLICATIONS INFORMATION in this case. Probe loads up to about 1mA maximum are supported in this configuration. Since V during the LTC6802-1 idle and shutdown modes, the thermistor drive is also shut off and thus power dissipa- tion minimized. Since V remains always on, the buffer REG op amp (LT6000 shown) is selected for its ultralow power consumption (10μ ...

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... During idle time when the LTC6802-1 WTB signal goes low, the external circuitry goes into a power down condition, reducing battery drain to a minimum. When not ...

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... APPLICATIONS INFORMATION PROVIDING HIGH-SPEED OPTO-ISOLATION OF THE SPI DATA-PORT Isolation techniques that are capable of supporting the 1Mbps data rate of the LTC6802-1 require more power on the isolated (battery) side than can be furnished by the V output of the LTC6802-1. To keep battery drain REG minimal, this means that a DC/DC function must be imple- mented along with a suitable data isolation circuit, such as shown in Figure 19 ...

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... The pinout of the LTC6802-1 was chosen to facilitate this physical separation. Figure 20 shows the DC voltage on each pin with respect to V battery cells are connected to the LTC6802-1. There is no more then 5.5V between any two adjacent pins. The pack- age body is used to separate the highest voltage (43.5V) from the lowest voltage (0V) ...

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... LTC6802-1’s ADC, which is about 1350Hz. This means that if wideband noise is applied to the LTC6802-1 input, the increase in noise seen at the digital output will be the same as an ADC with a wide bandwidth (such as a SAR) preceded by a perfect 1350Hz brickwall lowpass filter ...

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... LTC6802-1 PACKAGE DESCRIPTION 7.8 – 8.2 0.25 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 – 5.60* (.197 – .221) PARTING LINE 0.55 – 0.95** 0.10 – 0.25 (.004 – .010) (.022 – .037) 1.25 (.0492) REF NOTE: 1.DRAWING IS NOT A JEDEC OUTLINE 2. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 3 ...

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... Edit to Typical Application Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC6802-1 PAGE NUMBER 1 2 ...

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... S4 C3 100Ω C2FILTER 100nF PDZ7.5B DC2 3.3k 100Ω C1FILTER 100nF PDZ7.5B DC1 68021 TA02 3.3k COMMENTS Functionality equivalent to LTC6802-1, Allows for Parallel Communication Battery Stack Topologies www.linear.com ● 100Ω CSBI 100Ω MAIN SPI PORT SDO* 20Ω ...