UPC1853CT-02 NEC [NEC], UPC1853CT-02 Datasheet - Page 17
UPC1853CT-02
Manufacturer Part Number
UPC1853CT-02
Description
MATRIX SURROUND IC WITH I2C BUS
Manufacturer
NEC [NEC]
Datasheet
1.UPC1853CT-02.pdf
(76 pages)
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3. I
composed of 2 wires: serial clock line (SCL) and serial data line (SDA).
SCL (Serial Clock Line)
in the serial data.
SDA (Serial Data Line)
to the clock.
3.1 Data Transfer
3.1.1 Start condition
The PC1853 has serial bus function. This serial bus (I
The PC1853 has built-in I
The master CPU outputs serial clock to synchronize with the data. According to this clock, the PC1853 takes
Input level is compatible with CMOS.
Clock frequency is 0 to 100 kHz.
The master CPU outputs the data which is synchronized with serial clock. The PC1853 takes in this data according
Input level is compatible with CMOS.
Start condition is made by falling of SDA from “High” to “Low” during SCL is “High” as shown in Fig. 3-2.
When this start condition is received, the PC1853 takes in the data synchronizing with the clock after that.
2
C BUS INTERFACE
Fig. 3-1 Internal Equivalent Circuits of Interface Pin
2
C bus interface circuit, 9 rewritable registers (8 bits).
SDA
SCL
PC1853
R
2
P
C bus) is a double wired bus developed by Philips. It is
R
P
PC1853
17
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