CY7C0852V CYPRESS [Cypress Semiconductor], CY7C0852V Datasheet - Page 2
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CY7C0852V
Manufacturer Part Number
CY7C0852V
Description
FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY7C0852V.pdf
(29 pages)
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Document #: 38-06070 Rev. *D
Logic Block Diagram
Note:
OE
R/W
B0
B1
B2
B3
CE
CE
1.
DQ
DQ
DQ
DQ
CNTINT
A
CNT/MSK
ADS
CNTEN
CNTRST
CLK
0L
L
L
L
L
0L
1L
L
, 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits.
27L
18L
9L
0L
L
–A
L
L
–DQ
–DQ
–DQ
–DQ
17L
L
L
L
17L
8L
L
35L
26L
INT
9
9
9
9
18
L
Interrupt
[1]
Logic
Mask Register
Mirror Reg
Counter/
Address
Register
Addr.
Read
Back
MRST
Control
I/O
Address
Decode
Reset
Logic
Dual-Ported
RAM Array
True
TMS
TDI
TCK
Address
Decode
JTAG
Control
I/O
TDO
Mask Register
Mirror Reg
CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
Counter/
Register
Address
Addr.
Read
Back
Interrupt
Logic
18
INT
9
9
9
9
R
DQ
DQ
CNT/MSK
DQ
DQ
CNTRST
Page 2 of 29
CNTINT
27R
18R
A
9R
CNTEN
0R
0R
–DQ
–DQ
–DQ
CLK
–DQ
ADS
–A
R/W
CE
CE
OE
B0
B1
B2
B3
17R
R
R
R
R
35R
26R
17R
0R
1R
8R
R
R
R
R
R
R