AD7829 AD [Analog Devices], AD7829 Datasheet - Page 5

• Manufacturer Part Number: AD7829
• Description: 3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel Sampling ADCs
• Manufacturer: AD [Analog Devices]

Mnemonic
V
V
AGND
DGND
CONVST
EOC
CS
PD
RD
A0–A2
DB0–DB7
V
REV. B
IN1
DD
REF IN/OUT
to V
CONVST
DGND
EOC
IN8
DB2
DB1
DB0
RD
NC
CS
PD
10
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
(Not to Scale)
TOP VIEW
AD7822
Description
Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight
analog input channels respectively. The inputs have an input span of 2.5 V and 2 V depending on the sup-
ply voltage (V
default input range (V
± 10%). See Analog Input section of the data sheet for more information.
Positive supply voltage, 3 V ± 10% and 5 V ± 10%.
Analog Ground. Ground reference for track/hold, comparators, reference circuit and multiplexer.
Digital Ground. Ground reference for digital circuitry.
Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of
this signal. The falling edge of this signal places the track/hold in hold mode. The track/hold goes into track
mode again 120 ns after the start of a conversion. The state of the CONVST signal is checked at the end of
a conversion. If it is logic low, the AD7822/AD7825/AD7829 will power down. (See Operating Modes section
of the data sheet.)
Logic Output. The End of Conversion signal indicates when a conversion has finished. The signal can be used
to interrupt a microcontroller when a conversion has finished or latch data into a gate array. (See Parallel Inter-
face section of this data sheet.)
Logic input signal. The chip select signal is used to enable the parallel port of the AD7822, AD7825, and AD7829.
This is necessary if the ADC is sharing a common data bus with another device.
Logic Input. The Power-Down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low
places the AD7822 and AD7825 in Power-Down mode. The ADCs will power up when PD is brought logic
high again.
Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and
drive data onto the data bus. The signal is internally gated with the CS signal. Both RD and CS must be logic
low to enable the data bus.
Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the
RD signal goes low.
Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when
both RD and CS go active low.
Analog Input and Output. An external reference can be connected to the AD7822, AD7825, and AD7829 at this
pin. The on-chip reference is also available at this pin. When using the internal reference, this pin can be
left unconnected or, in some cases, it can be decoupled to AGND with a 0.1 F capacitor.
20
19
18
16
15
14
13
12
17
11
DB3
DB4
DB5
DB6
DB7
AGND
V
V
V
V
DD
REF IN
MID
IN1
/
OUT
DD
). This span may be centered anywhere in the range AGND to V
MID
unconnected) is AGND to 2 V (V
PIN FUNCTION DESCRIPTIONS
CONVST
DGND
PIN CONFIGURATIONS
EOC
DB0
DB2
V
DB1
PD
CS
RD
IN4
A1
A0
DIP/SOIC/TSSOP
12
10
11
1
2
3
4
5
6
7
8
9
(Not to Scale)
TOP VIEW
AD7825
–5–
23
22
20
19
18
16
24
21
17
15
14
13
DB3
DB4
DB5
DB6
DB7
AGND
V
V
V
V
V
V
DD
REF IN
MID
IN1
IN2
IN3
/
OUT
DD
= 3 V ± 10%) or AGND to 2.5 V (V
AD7822/AD7825/AD7829
CONVST
DGND
EOC
DB2
DB1
DB0
V
V
V
CS
RD
A2
A1
A0
IN8
IN7
IN6
10
11
12
13
14
1
2
3
4
5
6
7
8
9
(Not to Scale)
DD
TOP VIEW
AD7829
using the V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB3
DB4
DB5
DB6
DB7
AGND
V
V
V
V
V
V
V
V
DD
REF IN
MID
IN1
IN2
IN3
IN4
IN5
MID
DD
/
OUT
Pin. The
= 5 V