MT47H128M8HQ-37EL MICRON [Micron Technology], MT47H128M8HQ-37EL Datasheet - Page 84
![no-image](/images/no-image-200.jpg)
MT47H128M8HQ-37EL
Manufacturer Part Number
MT47H128M8HQ-37EL
Description
DDR2 SDRAM
Manufacturer
MICRON [Micron Technology]
Datasheet
1.MT47H128M8HQ-37EL.pdf
(131 pages)
- Current page: 84 of 131
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Extended Mode Register 3 (EMR3)
Figure 41: EMR3 Definition
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Notes:
The extended mode register 3 (EMR3) controls functions beyond those controlled by
the mode register. Currently all bits in EMR3 are reserved, as shown in Figure 41. The
EMR3 is programmed via the LM command and will retain the stored information until
it is programmed again or until the device loses power. Reprogramming the EMR will
not alter the contents of the memory array, provided it is performed correctly.
EMR3 must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time
tion. Violating either of these requirements could result in an unspecified operation.
E15
BA2
16
0
0
1
1
0
1. E16 (BA2) is only applicable for densities ≥1Gb, is reserved for future use, and must be
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-
1
E14
BA1
15
0
1
0
1
MRS
programmed to “0.”
served for future use and must be programmed to “0.”
BA0
14
Extended mode register (EMR2)
Extended mode register (EMR3)
Extended mode register (EMR)
0
n
An
Mode register (MR)
Mode Register Set
2
0
12
A12 A11
0
11
0
10
A10
0
9
A9
0
8
A8
0
7
A7 A6 A5 A4 A3
0
6
0
5
84
0
4
0
3
0
2
A2 A1 A0
0
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
1
MRD before initiating any subsequent opera-
Extended Mode Register 3 (EMR3)
0
0
Address bus
Extended mode
register (Ex)
1Gb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.
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