ICS307-02 ICST [Integrated Circuit Systems], ICS307-02 Datasheet - Page 5

• Manufacturer Part Number: ICS307-02
• Description: SERIALLY PROGRAMMABLE CLOCK SOURCE
• Manufacturer: ICST [Integrated Circuit Systems]

MDS 307-01/02 F
In te grated Circuit Systems
Bypass Mode
Configuring the ICS307
The ICS307 can be reprogrammed at any time during operation. If R6:0, V8:0, TTL, or C1:0 are changed, the
frequency will transition smoothly to the new value over about 1 ms, without glitches or short cycles. If S2:0 is
changed, it is possible to generate glitches on CLK1 and also on CLK2 for F1:0 = 1 1.
Changing F1:0 will generate glitches on CLK2.
Power up default values for ICS307-02
The input frequency will come from both outputs.
A warning about using the default configuration with input frequencies lower than 13.75 MHz
MSB
C1
0
0
C0
If R6:0 is programmed to 0000000, the PLL is powered down and bypassed; the reference frequency will
come from both CLK1 and CLK2. It is possible to generate glitches going into and out of this mode.
The ICS307 can be programmed to set the output functions and frequencies. The three data bytes are
written in DATA pin in this order:
C1 is loaded into the port first and R0 last.
R6:R0 Reference Divder Word (RDW)
V8:V0
S2:S0
F1:F0
TTL
C1:C0 Internal Load Capacitance for Crystal
The VCO will run only as low as its minimum frequency, which is guaranteed to be no more than 55 MHz.
So, in the powerup default condition, the PLL is guaranteed to lock to the input frequency down to 55/4 =
13.75 MHz. However, the part will typically run much slower. The typical minimum VCO frequency is about
30 - 40 MHz, depending on voltage, temperature, and lot variation; so in the powerup default setting, the
CLK2 output will be a minimum of 7.5 - 10 MHz even if the input frequency is lower than that. The output is
not locked to the reference input and so the frequency is not very stable and the phase noise is higher. In
this condition, the CLK2 output will accurately provide the reference frequency down to 0 Hz because this
signal path bypasses the PLL.
1
TTL
0
F1
VCO Divider Word (VDW)
Output Divider Select (OD)
Function of CLK2 Output
Duty Cycle Settings
0
F0
0
S2
1
●
S1
525 Ra ce Street, San Jose, CA 9512 6
1
LSB
S0
MSB
0
V8
0
V7
0
V6
5
0
V5
0
V4
1
S
ERIALLY
V3
0
V2
0
●
tel [phone]
P
LSB
V1
ROGRAMMABLE
MSB
0
V0
0
R6
0
R5
0
●
C
R4
ICS307-01/02
w w w. i c s t . c o m
LOCK
0
Revision 121304
R3
1
S
R2
OURCE
1
R1
0
LSB
R0