CY7C1302DV25_11 CYPRESS [Cypress Semiconductor], CY7C1302DV25_11 Datasheet

CY7C1302DV25_11

Manufacturer Part Number

CY7C1302DV25_11

Description

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture JTAG Interface

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7C1302DV25_11.pdf (25 pages)

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9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

Features

■

Configurations

CY7C1302DV25 – 512 K × 18

Cypress Semiconductor Corporation

Document Number: 38-05625 Rev. *D

Separate independent Read and Write data ports

❐

167-MHz clock for high bandwidth

❐

2-word burst on all accesses

Double Data Rate (DDR) interfaces on both Read and Write

ports (data transferred at 333 MHz) @ 167 MHz

Two input clocks (K and K) for precise DDR timing

❐

Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches.

Single multiplexed address input bus latches address inputs

for both Read and Write ports

Separate Port Selects for depth expansion

Synchronous internally self-timed writes

2.5 V core power supply with HSTL Inputs and Outputs

Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

Variable drive HSTL output buffers

Expanded HSTL output voltage (1.4 V–1.9 V)

JTAG Interface

Supports concurrent transactions

2.5 ns Clock-to-Valid access time

SRAM uses rising edges only

•

198 Champion Court

9-Mbit Burst of Two Pipelined SRAMs

Functional Description

The CY7C1302DV25 is a 2.5 V Synchronous Pipelined SRAM

equipped with QDR™ architecture. QDR architecture consists of

two separate ports to access the memory array. The Read port

has dedicated data outputs to support Read operations and the

Write Port has dedicated data inputs to support Write operations.

Access to each port is accomplished through a common address

bus. The Read address is latched on the rising edge of the

K clock and the Write address is latched on the rising edge of

K clock. QDR has separate data inputs and data outputs to

completely eliminate the need to “turn-around” the data bus

required with common I/O devices. Accesses to the

CY7C1302DV25 Read and Write ports are completely

independent of one another. All accesses are initiated

synchronously on the rising edge of the positive input clock (K).

In order to maximize data throughput, both Read and Write ports

are equipped with DDR interfaces. Therefore, data can be

transferred into the device on every rising edge of both input

clocks (K and K) and out of the device on every rising edge of

the output clock (C and C, or K and K in a single clock domain)

thereby maximizing performance while simplifying system

design. Each address location is associated with two 18-bit

words that burst sequentially into or out of the device.

Depth expansion is accomplished with a Port Select input for

each port. Each Port Select allows each port to operate

independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

•

San Jose

with QDR™ Architecture

CA 95134-1709

CY7C1302DV25

Revised May 9, 2011

•

408-943-2600

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CY7C1302DV25_11 Summary of contents

Page 1

Burst of Two Pipelined SRAMs with QDR™ Architecture Features Separate independent Read and Write data ports ■ Supports concurrent transactions ❐ 167-MHz clock for high bandwidth ■ 2.5 ns Clock-to-Valid access time ❐ 2-word burst on all accesses ■ ...

Page 2

Logic Block Diagram - CY7C1302DV25 D [17:0] 18 Address A Register (17: CLK K Gen. Vref Control WPS Logic BWS 0 BWS 1 Document Number: 38-05625 Rev. *D Write Write Data Reg Data Reg Address Register 256Kx18 256Kx18 ...

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Contents Selection Guide ................................................................ 4 Pin Configuration ............................................................. 4 165-ball FBGA (13 × 15 × 1.4 mm) Pinout .................. 4 Pin Definitions .................................................................. 4 Introduction ....................................................................... 5 Functional Overview .................................................... 5 Read Operations ......................................................... 6 Write Operations ......................................................... 6 Byte ...

Page 4

Selection Guide Maximum Operating Frequency Maximum Operating Current Pin Configuration Gnd/144M NC/36M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 ...

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Pin Definitions (continued) Name I/O RPS Input- Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When ...

Page 6

Read Operations The CY7C1302DV25 is organized internally as 2 arrays of 256 K × 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of ...

Page 7

Application Example [1] Note 1. The above application shows 4 QDR-I being used. Document Number: 38-05625 Rev. *D CY7C1302DV25 Page [+] Feedback ...

Page 8

Truth Table [ Operation Write Cycle: Load address on the rising edge of K clock; input write data on K and K rising edges. Read Cycle: Load address on the rising edge of K clock; ...

Page 9

IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 2.5 V I/O logic ...

Page 10

IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when ...

Page 11

TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 38-05625 Rev. *D [9] 1 SELECT DR-SCAN ...

Page 12

TAP Controller Block Diagram Selection TDI Circuitry TCK TMS TAP Electrical Characteristics [10, 11, 12] Over the Operating Range Parameter Description V Output HIGH Voltage OH1 V Output HIGH Voltage OH2 V Output LOW Voltage OL1 V Output LOW Voltage ...

Page 13

TAP AC Switching Characteristics [13, 14] Over the Operating Range Parameter t TCK Clock Cycle Time TCYC t TCK Clock Frequency TF t TCK Clock HIGH TH t TCK Clock LOW TL Set-up Times t TMS Set-up to TCK Clock ...

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TAP Timing and Test Conditions 1.  TDO = 50  (a) GND Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Identification Register Definitions Instruction Field ...

Page 15

Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Instruction Codes Instruction Code EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. ...

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Boundary Scan Order Bit # Bump ID Bit # 11P 36 10 ...

Page 17

Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature .............................. –65 ° 150 °C Ambient Temperature with Power Applied ........................................ –55 ° 125 °C Supply ...

Page 18

Thermal Resistance [23] Parameter Description  Thermal Resistance JA (Junction to Ambient)  Thermal Resistance JC (Junction to Case) Capacitance [23] Parameter Description C Input Capacitance IN C Clock Input Capacitance CLK C Output Capacitance O AC Test Loads and ...

Page 19

Switching Characteristics (continued) [24] Over the Operating Range Cypress Consortium Parameter Parameter Hold Times t t Address Hold after Clock (K and K) Rise Control Signals Hold after Clock (K and K) Rise HC HC (RPS, ...

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Switching Waveforms [28, 29, 30] READ WRITE READ RPS tSC tHC WPS D10 D11 D30 ...

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Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress ...

Page 22

Package Diagram Document Number: 38-05625 Rev. *D CY7C1302DV25 51-85180 *C Page [+] Feedback ...

Page 23

Acronyms Acronym Description BWS byte write select DDR double data rate FBGA fine-pitch ball grid array HSTL high-speed transceiver logic I/O Input/output JTAG joint test action group LSB least significant bit MSB most significant bit NC no connect QDR quad ...

Page 24

Document History Page Document Title: CY7C1302DV25, 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Document Number: 38-05625 Submission Orig. of REV. ECN NO. Date Change ** 253010 See ECN *A 436864 See ECN *B 2896202 03/19/2010 *C 3122015 12/28/2010 ...

Page 25

Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive cypress.com/go/automotive Clocks & ...

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