ICS85408BG ICST [Integrated Circuit Systems], ICS85408BG Datasheet - Page 7

• Manufacturer Part Number: ICS85408BG
• Description: LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
• Manufacturer: ICST [Integrated Circuit Systems]

W
LVDS D
A general LVDS interface is shown in Figure 2. In a 100 differ-
ential transmission line environment, LVDS drivers require a
matched load termination of 100 across near the receiver in-
85408BG
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
IRING THE
RIVER
D
Integrated
Circuit
Systems, Inc.
IFFERENTIAL
T
ERMINATION
3.3V
LVDS_DRIVER
F
I
IGURE
NPUT TO
Single Ended Clock Input
1. S
A
A
F
INGLE
PPLICATION
www.icst.com/products/hiperclocks.html
CCEPT
IGURE
Zo = 50 Ohm
Zo = 50 Ohm
E
C1
0.1u
2. T
NDED
S
V_REF
INGLE
D
DD
YPICAL
S
/2 is
IFFERENTIAL
IGNAL
E
7
LVDS D
I
NDED
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
D
1K
R1
1K
R2
RIVING
VDD
L
RIVER
EVELS
R1
100
D
-
CLK
nCLK
TO
IFFERENTIAL
T
-LVDS C
ERMINATION
I
NPUT
CLK
nCLK
LOCK
3.3V
DD
= 3.3V, V_REF should be 1.25V
HiPerClockS
L
D
OW
ISTRIBUTION
ICS85408
S
KEW
REV. A APRIL 25, 2005
, 1-
C
TO
HIP
-8