ICS8705 ICST [Integrated Circuit Systems], ICS8705 Datasheet - Page 11

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ICS8705

Manufacturer Part Number
ICS8705
Description
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet

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F
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D
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
V
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
PP
IGURE
IFFERENTIAL
and V
3.3V
3C. H
3A. H
1.8V
CMR
LVPECL
input requirements. Figures 3A to 3D show inter-
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V LVPECL D
ICS H
I
I
P
P
Integrated
Circuit
Systems, Inc.
C
ER
ER
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
C
Zo = 50 Ohm
Zo = 50 Ohm
C
I
P
LOCK
LOCK
ER
C
I
S CLK/
NPUT
S CLK/
LOCK
RIVER
S LVHSTL D
R1
50
3.3V
R3
125
I
R1
84
NTERFACE
SWING
N
N
CLK I
CLK I
R2
50
R4
125
R2
84
and V
CLK
nCLK
NPUT
NPUT
CLK
nCLK
www.icst.com/products/hiperclocks.html
3.3V
OH
3.3V
RIVER
HiPerClockS
Input
must meet the
HiPerClockS
Input
D
D
RIVEN BY
RIVEN BY
Z
ERO
11
F
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
F
D
IGURE
IGURE
ELAY
3.3V
3.3V
3D. H
3B. H
LVDS_Driv er
, D
LVPECL
IFFERENTIAL
3.3V LVDS D
3.3V LVPECL D
I
I
P
P
Zo = 50 Ohm
Zo = 50 Ohm
ER
ER
C
C
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
S CLK/
S CLK/
RIVER
-
TO
R1
50
RIVER
R3
50
-LVCMOS/LVTTL
N
N
C
R2
50
CLK I
CLK I
R1
100
LOCK
CLK
nCLK
3.3V
ICS8705
NPUT
NPUT
HiPerClockS
REV. G JUNE 16, 2004
G
Input
CLK
nCLK
ENERATOR
D
D
3.3V
RIVEN BY
RIVEN BY
Receiv er

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