ICS8705 ICST [Integrated Circuit Systems], ICS8705 Datasheet - Page 12

• Manufacturer Part Number: ICS8705
• Description: ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
• Manufacturer: ICST [Integrated Circuit Systems]

L
The schematic of the ICS8705 layout example is shown in
Figure 4A. The ICS8705 recommended PCB board layout
for this example is shown in Figure 4B. This layout example is
used as a general guideline. The layout in the actual system will
8705BY
AYOUT
VDD
VDD=3.3V or 2.5V
Logic Input Pin Examples
VDD
Driv er_LVCMOS
RU1
1K
RD1
Not Install
G
Ro ~ 7 Ohm
Set Logic
Input to
'1'
UIDELINE
To Logic
Input
pins
R4
Integrated
Circuit
Systems, Inc.
43
VDD
F
IGURE
Zo = 50
RU2
Not Install
RD2
1K
Set Logic
Input to
'0'
4A. ICS8705 LVCMOS C
To Logic
Input
pins
R5
1K
VDD
SEL0
SEL1
R4
10 - 15
1K
10u
R7
C16
www.icst.com/products/hiperclocks.html
(U1-9)
1
2
3
4
5
6
7
8
U1
ICS8705
0.01u
0.1uF
C11
SEL0
SEL1
CLK0
nc
CLK1
nCLK1
CLK_SEL
MR
C2
VDDA
VDD
Z
ERO
(U1-12)
LOCK
12
0.1uF
depend on the selected component types, the density of the
components, the density of the traces, and the stack up of the
P.C. board.
D
C3
ELAY
G
(U1-16)
ENERATOR
VDDO
VDDO
, D
GND
GND
R1
0.1uF
Q5
Q4
Q3
Q2
C4
VDD
R2
IFFERENTIAL
(U1-20)
24
23
22
21
20
19
18
17
43
S
CHEMATIC
43
0.1uF
C5
(U1-24)
Zo = 50
Zo = 50
E
-
XAMPLE
TO
0.1uF
C6
-LVCMOS/LVTTL
C
(U1-28)
LOCK
0.1uF
ICS8705
C1
REV. G JUNE 16, 2004
G
(U1-32)
ENERATOR
0.1uF
C7