ICS9159M-05 ICST [Integrated Circuit Systems], ICS9159M-05 Datasheet - Page 3
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ICS9159M-05
Manufacturer Part Number
ICS9159M-05
Description
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet
1.ICS9159M-05.pdf
(7 pages)
Note:
1. Internally pulled-up
Pin Descriptions
3, 11, 23, 17
NUMBER
15, 16, 18,
19,21, 22
8, 20, 26
6, 7, 9
27, 28
PIN
4, 5
24
25
10
12
13
14
2
1
GND
CPU(0:2)
STOP#
VDD
X1
X2
FS(0:1)
ECPU
BUS(0:5)
DOZE#
BSEL#
KEYBD
DISK
REF (0:1)
PIN NAME
1
1
1
TYPE
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
12 MHz fixed clock (with 14.318 MHz input).
capacitance and feedback bias for a 4-20 MHz XTAL, normally 14.318 MHz.
Ground for logic, CPU and fixed frequency output buffers.
shown in the table.
Stop Clock. Stops all CPU clock outputs and forces them to a logic low level
synchronously with their next low level transition.
24 MHz fixed clock (with 14.318 MHz input).
Early CPU clock. Transition precedes CPU clocks.
Bus clock outputs are fixed at 1/2 the PCLK frequency.
Power for logic, CPU and fixed frequency output buffers.
XTAL or external reference frequency input. This input includes XTAL load
XTAL output which includes XTAL load capacitance.
Processor clock outputs which are a multiple of the input reference frequency as
Frequency multiplier select pins. See table below. These inputs have internal pull-
up devices.
Doze mode control. Reduces CPU and BUS clock frequencies by 1/2 when low.
BUS select for BSEL = 0, BUS = CPU/2
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.
for BSEL = 1, BUS = CPU
3
DESCRIPTION
ICS9159-05