CY7C1360B CYPRESS [Cypress Semiconductor], CY7C1360B Datasheet - Page 28

• Manufacturer Part Number: CY7C1360B
• Description: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05291 Rev. *C
Switching Waveforms
Read/Write Cycle Timing
Notes:
24. The data bus (Q) remains in high-Z following a Write cycle, unless a new Read access is initiated by ADSP or ADSC .
25. GW is HIGH.
Data Out (Q)
Data In (D)
ADDRESS
ADSC
ADSP
BWE,
ADV
BW
CLK
OE
CE
X
A1
High-Z
High-Z
t ADS
t CES
t AS
A2
t ADH
t CEH
t CH
t AH
Back-to-Back READs
t CYC
t CLZ
[22, 24, 25]
Q(A1)
t CL
(continued)
t CO
Q(A2)
t OEHZ
t WES
t DS
D(A3)
Single WRITE
A3
t DH
t WEH
DON’T CARE
A4
t OELZ
UNDEFINED
Q(A4)
BURST READ
Q(A4+1)
Q(A4+2)
Q(A4+3)
CY7C1360B
CY7C1362B
D(A5)
A5
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Back-to-Back
WRITEs
D(A6)
A6