CY7C1382D CYPRESS [Cypress Semiconductor], CY7C1382D Datasheet - Page 25

• Manufacturer Part Number: CY7C1382D
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Document Number: 38-05543 Rev. *I
Notes
32. On this diagram, when CE is LOW: CE
33. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
34. GW is HIGH.
Data Out (Q)
Data In (D)
ADDRESS
ADSP
ADSC
BWE,
ADV
BW
CLK
OE
CE
X
A1
High-Z
High-Z
t ADS
t CES
t AS
A2
t ADH
t CEH
t CH
t AH
Back-to-Back READs
t CYC
t CLZ
Q(A1)
t CL
t CO
(continued)
1
is LOW, CE
Q(A2)
t OEHZ
Figure 12. Read/Write Cycle Timing
2
t WES
t DS
D(A3)
Single WRITE
is HIGH and CE
A3
t DH
t WEH
DON’T CARE
A4
3
is LOW. When CE is HIGH: CE
t OELZ
UNDEFINED
Q(A4)
[32, 33, 34]
BURST READ
Q(A4+1)
1
is HIGH or CE
Q(A4+2)
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
2
Q(A4+3)
is LOW or CE
D(A5)
A5
3
is HIGH.
Back-to-Back
WRITEs
D(A6)
A6
Page 25 of 33
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