CAT24C08 CATALYST [Catalyst Semiconductor], CAT24C08 Datasheet - Page 6

• Manufacturer Part Number: CAT24C08
• Description: 1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

WRITE OPERATIONS
Byte Write
In Byte Write mode, the Master sends the START condi-
tion and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge,
the Master sends the byte address that is to be written
into the address pointer of the CAT24Cxx. After receiv-
ing another acknowledge from the Slave, the Master
transmits the data byte to be written into the addressed
memory location. The CAT24Cxx device will acknowl-
edge the data byte and the Master generates the STOP
condition, at which time the device begins its internal
Write cycle to nonvolatile memory (Figure 5). While this
internal cycle is in progress (t
be tri-stated and the CAT24Cxx will not respond to any
request from the Master device (Figure 6).
Page Write
The CAT24Cxx writes up to 16 bytes of data in a single
write cycle, using the Page Write operation (Figure 7).
The Page Write operation is initiated in the same manner
as the Byte Write operation, however instead of termi-
nating after the data byte is transmitted, the Master is
allowed to send up to fifteen additional bytes. After each
byte has been transmitted the CAT24Cxx will respond
with an acknowledge and internally increments the four
low order address bits. The high order bits that define
the page address remain unchanged. If the Master
transmits more than sixteen bytes prior to sending the
STOP condition, the address counter ‘wraps around’ to
the beginning of page and previously transmitted data
will be overwritten. Once all sixteen bytes are received
and the STOP condition has been sent by the Master,
the internal Write cycle begins. At this point all received
data is written to the CAT24Cxx in a single write cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the host’s
write operation, the CAT24Cxx initiates the internal write
cycle. TheACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24Cxx is still
busy with the write operation, NoACK will be returned. If
the CAT24Cxx has completed the internal write operation,
an ACK will be returned and the host can then proceed
with the next read or write operation.
Doc. No. 1115, Rev. C
CAT24C01/02/04/08/16
WR
), the SDA output will
6
Hardware Write Protection
With the WPpin held HIGH, the entire memory is protected
against Write operations. If the WP pin is left floating or
is grounded, it has no impact on the operation of the
CAT24Cxx. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first
data byte (Figure 8). If the WP pin is HIGH during the
strobe interval, the CAT24Cxx will not acknowledge the
data byte and the Write request will be rejected.
Delivery State
The CAT24Cxx is shipped erased, i.e., all bytes are
FFh.
Characteristics subject to change without notice
© 2006 by Catalyst Semiconductor, Inc.