VSC8021FC VITESSE [Vitesse Semiconductor Corporation], VSC8021FC Datasheet - Page 2

no-image

VSC8021FC

Manufacturer Part Number
VSC8021FC
Description
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
Manufacturer
VITESSE [Vitesse Semiconductor Corporation]
Datasheet
Page 2
2.5Gb/s SONET-Compatible
8-Bit MUX/DEMUX Chipset
work with each other. The Phase Detector and the Phase Adjust Circuit work together to adjust the internal
clock CLK8 to make sure the set up and hold conditions are met for the internal registers. CLK8 is derived from
CLKI and the RCLK is a non-phase varying byte clock output. The edge sensitive SYNC signal is simply the
control signal that enables the Phase Detector circuitry.
is the internal byte clock derived from CLKI, phase-adjusted if SYNC is enabled. The RCLK is a non-phase-
adjusted divided-by-8 clock generated from CLKI. The phase of RCLK, RCLKN is not affected by the self-
adjusting circuitry, therefore it can be used as a system reference clock. RCLK, RCLKN can be used by the sys-
tem designer to generate BYCLK, BYCLKN. The self-positioning timer and RCLK, RCLKN allow for the cre-
ation of very tight parallel data timing for the VSC8021.
An internal Phase Detector and Phase Adjust Circuit are used to facilitate the two asynchronous circuits to
As a summary, the CLKI is the high-speed clock input. The BYCLK is the external byte clock. The CLK8
Byte Clock
Clock Inputs
High Speed
Inputs
Parallel
Data
BYCLKN
BYCLK
CLKIN
SYNC
CLKI
D1N
D8N
D1
D8
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
VITESSE
SEMICONDUCTOR CORPORATION
Figure 1: VSC8021 Block Diagram
8
Adjust
Phase
Internet: www.vitesse.com
8
Multiplexer
8:1
Generator
Timing
VSC8021/VSC8022
DO
DON
CLK8N
RCLK
RCLKN
CO
CON
ERR
CLK8
Serial Data Output
High Speed
Clock
Phase Adjustable
Byte Clock Output
Independent
Byte Clock Output
Data Sheet
G52028-0, Rev 4.1
05/25/01

Related parts for VSC8021FC