CY7C1470V25_11 CYPRESS [Cypress Semiconductor], CY7C1470V25_11 Datasheet
CY7C1470V25_11
Related parts for CY7C1470V25_11
CY7C1470V25_11 Summary of contents
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TM 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL Architecture Features Pin-compatible and functionally equivalent to ZBT™ ■ Supports 250-MHz bus operations with zero wait states ■ Available speed grades are 250, 200 ...
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Logic Block Diagram - CY7C1472V25 (4 M × 18) A0, A1, A REGISTER 0 MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ CE1 CE2 CE3 ZZ Logic Block Diagram - CY7C1474V25 (1 M ...
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Contents Selection Guide ................................................................ 4 Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 6 Functional Overview ........................................................ 8 Single Read Accesses ................................................ 8 Burst Read Accesses .................................................. 8 Single Write Accesses ................................................. 8 Burst Write Accesses .................................................. 9 Sleep Mode ................................................................. ...
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Selection Guide Maximum access time Maximum operating current Maximum CMOS standby current Pin Configurations DQPc 1 DQc 2 DQc DDQ DQc 6 DQc 7 DQc 8 DQc DDQ 11 ...
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Pin Configurations (continued) 165-ball FBGA (15 × 17 × 1.4 mm) Pinout NC/576M NC/1G CE2 A C DQP DDQ DDQ ...
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Pin Configurations (continued) 209-ball FBGA (14 × 22 × 1.76 mm) Pinout DQg DQg A B DQg DQg BWS C DQg DQg BWS D DQg DQg DQPg DQPc V DDQ F DQc DQc ...
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Pin Definitions (continued) Pin Name I/O Type ADV/LD Input- Advance/load input used to advance the on-chip address counter or load a new address. synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a ...
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Pin Definitions (continued) Pin Name I/O Type NC(144M, – These pins are not connected. They will be used for expansion to the 144M, 288M, 576M and 288M, 1G densities. 576M, 1G) ZZ Input- ZZ “sleep” input. This active HIGH input ...
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Because the CY7C1470V25/CY7C1472V25/CY7C1474V25 are common I/O devices, data should not be driven into the device while the outputs are active. The output enable (OE) can be deasserted HIGH before ...
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Truth Table [ Address Operation Used Deselect cycle None Continue deselect cycle None Read cycle (begin burst) External Read cycle (continue burst) Next NOP/dummy read (begin burst) External Dummy read (continue burst) Next Write ...
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Function (CY7C1472V25) Read Write – no bytes written Write byte a – (DQ and DQP ) a a Write byte b – (DQ and DQP ) b b Write both bytes Function (CY7C1474V25) Read Write – no bytes written Write ...
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IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470V25/CY7C1472V25/CY7C1474V25 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These ...
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Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Upon power-up, the instruction register is loaded ...
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CLK captured in the boundary scan register. Once the data is captured possible to shift out the data by putting the TAP into the Shift-DR ...
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V TAP AC Test Conditions Input pulse levels................................................V Input rise and fall time .....................................................1 ns Input timing reference levels........................................ 1.25 V Output reference levels ............................................... 1.25 V Test load termination supply voltage ........................... 1.25 V 2.5 V TAP AC ...
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Scan Register Sizes Register Name Instruction Bypass ID Boundary scan order–165-ball FBGA Boundary scan order–209-ball BGA Identification Codes Instruction Code EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to ...
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Boundary Scan Exit Order (2 M × 36) Bit # 165-ball ID Bit # ...
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Boundary Scan Exit Order (1 M × 72) Bit # 209-ball ID Bit # ...
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Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Supply voltage on ...
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Electrical Characteristics (continued) [12, 13] Over the Operating Range Parameter Description I Automatic CE Max V SB3 power-down V current—CMOS inputs Automatic CE Max V SB4 power-down V current—TTL inputs Capacitance [15] Parameter Description C ...
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AC Test Loads and Waveforms 2.5 V I/O Test Load OUTPUT OUTPUT = 50 1. (a) 1.8 V I/O Test Load OUTPUT OUTPUT = 50 ...
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Switching Characteristics [16, 17] Over the Operating Range Parameter Description [18 (typical) to the first access read or write Power CC Clock t Clock cycle time CYC F Maximum operating frequency MAX t Clock HIGH CH t Clock ...
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Switching Waveforms [22, 23, 24] Read/Write/Timing CYC CLK CENS CENH CL CH CEN t t CES CEH CE ADV/ ADDRESS Data In-Out ...
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Switching Waveforms (continued) NOP, STALL and DESELECT Cycles 1 2 CLK CEN CE ADV/LD WE BWx A1 A2 ADDRESS Data In-Out (DQ) WRITE READ D(A1) Q(A2) [28, 29] ZZ Mode Timing CLK ZZ I SUPPLY ALL INPUTS (except ZZ) Outputs ...
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Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available.For a complete listing of all options, visit the Cypress website ...
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Package Diagrams Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050 Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85165 Document Number: 38-05290 Rev. *L CY7C1470V25 CY7C1472V25 CY7C1474V25 51-85050 *D 51-85165 *B Page ...
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Figure 3. 209-ball FPBGA (14 × 22 × 1.76 mm), 51-85167 Document Number: 38-05290 Rev. *L CY7C1470V25 CY7C1472V25 CY7C1474V25 51-85167 *A Page [+] Feedback ...
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Acronyms Acronym Description CE chip enable CEN clock enable FPBGA fine-pitch ball grid array JTAG Joint Test Action Group NoBL No Bus Latency OE output enable TCK test clock TDI test data input TMS test mode select TDO test data ...
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Document History Page Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05290 Orig. of REV. ECN No. Issue Date Change ** 114677 08/06/02 PKS *A 121519 01/27/03 ...
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Document History Page (continued) Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05290 *I 472335 See ECN VKN *J 2898958 03/25/10 NJY *K 3054137 10/10/2010 NJY *L ...
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