AD9518-1A-PCBZ AD [Analog Devices], AD9518-1A-PCBZ Datasheet
AD9518-1A-PCBZ
Related parts for AD9518-1A-PCBZ
AD9518-1A-PCBZ Summary of contents
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... REF2 DIVIDER AND MUXs DIV/Φ LVPECL DIV/Φ LVPECL DIV/Φ LVPECL SERIAL CONTROL PORT AD9518-1 AND DIGITAL LOGIC Figure 1. AD9516 and AD9517 are similar to the is available in a 48-lead LFCSP and can be is specified for operation over the industrial is used throughout the data sheet to refer to all the members of the family ...
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... MSB/LSB First Transfers ........................................................... 41 Thermal Performance .................................................................... 44 Control Registers ............................................................................ 45 Control Register Map Overview .............................................. 45 Control Register Map Descriptions ......................................... 47 Applications Information .............................................................. 59 Frequency Planning Using the AD9518 .................................. 59 Using the AD9518 Outputs for ADC Clock Applications .... 59 LVPECL Clock Distribution ..................................................... 60 Outline Dimensions ....................................................................... 61 Ordering Guide .......................................................................... 61 Rev Page Data Sheet ...
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... Changes to Table 44 ........................................................................ 48 Changes to Table 45 ........................................................................ 55 Changes to Table 46 ........................................................................ 57 Changes to Table 47 ........................................................................ 58 Changes to Table 48 ........................................................................ 59 Added Frequency Planning Using the AD9518 Section ............ 60 Changes to LVDS Clock Distribution Section ............................ 61 Changes to Figure 52 and Figure 54; Added Figure 53 .............. 61 Added Exposed Paddle Notation to Outline Dimensions; Changes to Ordering Guide ........................................................... 62 9/07— ...
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... AD9518-1 SPECIFICATIONS Typical values are given for S_LVPECL Minimum and maximum values are given over full V POWER SUPPLY REQUIREMENTS Table 1. Parameter S_LVPECL V CP RSET Pin Resistor CPRSET Pin Resistor BYPASS Pin Capacitor PLL CHARACTERISTICS Table 2. Parameter VCO (ON-CHIP) Frequency Range ...
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... Register 0x017[1:0] = 10b; Register 0x018[ Rev Page pin voltage charge pump power supply voltage CP = 5.1 kΩ RSET = < V − 0 < V − 0 VCXO/VCO Feedback Divider N— AD9518-1 section ) is an approxi- PFD ...
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... AD9518-1 CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Input Sensitivity, Differential Input Level, Differential Input Common-Mode Voltage Input Common-Mode Range, V CMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance 1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V CLOCK OUTPUTS Table 4 ...
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... Internal VCO; direct to LVPECL output −46 dBc/Hz −76 dBc/Hz −104 dBc/Hz −123 dBc/Hz −140 dBc/Hz −146 dBc/Hz −47 dBc/Hz −77 dBc/Hz −105 dBc/Hz −124 dBc/Hz −141 dBc/Hz −146 dBc/Hz −54 dBc/Hz −78 dBc/Hz −106 dBc/Hz −125 dBc/Hz −141 dBc/Hz −146 dBc/Hz Rev Page AD9518-1 ...
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... AD9518-1 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER VCO = 2.46 GHz; LVPECL = 491.52 MHz; PLL LBW = 55 kHz VCO = 2.46 GHz; LVPECL = 122.88 MHz; PLL LBW = 55 kHz VCO = 2.46 GHz; LVPECL = 61.44 MHz; PLL LBW = 55 kHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9 ...
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... Calculated from SNR of ADC method; DCC on Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO; uses rising edge of clock signal 210 fs rms Calculated from SNR of ADC method Rev Page AD9518-1 ...
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... AD9518-1 SERIAL CONTROL PORT Table 13. Parameter CS (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN INPUT) Input Logic 1 Voltage ...
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... CLK input selected to VCO selected 75 mW PLL off to PLL on, normal operation; no reference enabled 30 mW Divider bypassed to divide-by-2 to divide-by-32 160 mW No LVPECL output on to one LVPECL output on, independent of frequency 90 mW Second LVPECL output turned on, same channel Rev Page AD9518-1 ...
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... AD9518-1 TIMING DIAGRAMS t CLK CLK t PECL Figure 2. CLK/ CLK to Clock Output Timing, DIV = 1 DIFFERENTIAL 80% 20 Figure 3. LVPECL Timing, Differential Rev Page Data Sheet LVPECL t FP ...
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... LFCSP −0 0 Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-2. −0 0 −0 0.3 V ESD CAUTION S 150°C −65°C to +150°C 300°C Rev Page AD9518-1 1 θ Unit JA 24.7 °C/W ...
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... I Differential clock input 12 I Differential clock input 1 PIN INDICATOR VCP STATUS 5 AD9518-1 6 TOP VIEW SYNC 7 (Not to Scale BYPASS CLK 11 CLK 12 CONNECTED TO GROUND FOR PROPER OPERATION. Figure 4. Pin Configuration Mnemonic Description REFMON Reference Monitor (Output). This pin has multiple selectable outputs; see Table 44, Register 0x01B ...
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... REFIN (REF1) Along with REFIN, this is the self-biased differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1. GND Ground. The external paddle on the bottom of the package must be connected to ground for proper operation. Rev Page AD9518-1 ...
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... AD9518-1 TYPICAL PERFORMANCE CHARACTERISTICS 300 3 CHANNELS—6 LVPECL 280 260 240 220 200 3 CHANNELS—3 LVPECL 180 160 2 CHANNELS—2 LVPECL 140 120 1 CHANNEL—1 LVPECL 100 0 500 1000 1500 FREQUENCY (MHz) Figure 5. Current vs. Frequency, Direct to Output, LVPECL Outputs ...
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... TIME (ns) Figure 14. LVPECL Output (Differential) at 100 MHz 1.0 0.6 0.2 –0.2 –0.6 –1 TIME (ns) Figure 15. LVPECL Output (Differential) at 1600 MHz 1600 1400 1200 1000 800 FREQUENCY (GHz) Figure 16. LVPECL Differential Swing vs. Frequency, Using a Differential Probe Across the Output Pair AD9518 ...
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... AD9518-1 –70 –80 –90 –100 –110 –120 –130 –140 –150 10k 100k 1M FREQUENCY (Hz) Figure 17. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2650 MHz –70 –80 –90 –100 –110 –120 –130 –140 –150 10k 100k 1M FREQUENCY (Hz) Figure 18. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2475 MHz – ...
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... NOTE: 375UI MAX AT 10Hz OFFSET IS THE 0.1 0.01 10M 100M Rev Page AD9518-1 10k 100k 1M 10M FREQUENCY (Hz) OC-48 OBJECTIVE MASK AD9518 f OBJ MAXIMUM JITTER THAT CAN BE GENERATED BY THE TEST EQUIPMENT. FAILURE POINT IS GREATER THAN 375UI. 0 100 JITTER FREQUENCY (kHz) Figure 26. GR-253 Jitter Tolerance Plot 100M ...
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... AD9518-1 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter ...
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... PRESCALER COUNTERS N DELAY N DIVIDER DIVIDE DIVIDE DIVIDE DIVIDE Figure 27. Detailed Block Diagram Rev Page AD9518-1 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS OUT0 OUT0 LVPECL OUT1 ...
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... High Frequency Clock Distribution—CLK or External VCO > 1600 MHz The AD9518 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide- by-6) ...
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... PROGRAMMABLE A/B N DELAY PRESCALER COUNTERS N DIVIDER DIVIDE DIVIDE DIVIDE DIVIDE Rev Page AD9518-1 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS OUT0 OUT0 LVPECL OUT1 OUT1 ...
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... BYPASS REGULATOR (LDO) LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9518-1 Table 23. Settings When Using an Internal VCO Register 0x010[1:0] = 00b 0x010 to 0x01D 0x018[0] = 0b, 0x232[ 0x1E0[2:0] 0x1E1[ 0x1E1[ 0x018[0] = 1b, 0x232[ GND RSET REFMON DISTRIBUTION REFERENCE ...
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... VCO/VCXO being used. Table 26. Setting the PFD Polarity Register 0x010[ 0x010[ After the appropriate register values are programmed, Register 0x232 must be set to 0x01 for the values to take effect. Rev Page AD9518-1 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE ...
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... ADIsimCLK™ (V1.2 or later free program that can help with the design and exploration of the capabilities and features of the AD9518, including the design of the PLL loop filter available at www.analog.com/clocks. Phase Frequency Detector (PFD) The PFD takes inputs from the R counter and N counter and ...
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... PLL is powered down, or when the differential reference input is not selected. The single-ended buffers power down when the PLL is powered down, and when their individual power down registers are set. When the differential mode is selected, the single-ended inputs are powered down. Rev Page AD9518 ...
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... P can 16, or 32. Prescaler The prescaler of the AD9518 a fixed divide (FD) mode and a dual modulus (DM) mode where the prescaler divides by P and ( and 3, 4 and 5, 8 and 9, 16 and 17 and 33}. The prescaler modes of operation are given in Table 44, Register 0x016[2:0] ...
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... DM 200 2000 DM 270 2700 not allowed (2700 ÷ 8 > 300 MHz not allowed (A > not allowed). 2710 2710 also permitted. Rev Page AD9518-1 AD9518 B counter is bypassed (B = 1), the A counter ...
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... PLL off feedback input for an external VCO/VCXO using the internal PLL when the internal VCO is not used. The CLK/ CLK input can be used for frequencies up to 2.4 GHz. Rev Page Data Sheet AD9518-1 110µA DLD V LD OUT ...
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... HIGH IMPEDANCE YES NO DLD == HIGH Figure 38. Flow Chart of Automatic/Internal Holdover Mode Rev Page AD9518-1 LOOP OUT OF LOCK. DIGITAL LOCK DETECT SIGNAL GOES LOW WHEN THE LOOP LEAVES LOCK AS DETERMINED BY THE PHASE DIFFERENCE AT THE INPUT OF THE PFD. ANALOG LOCK DETECT PIN INDICATES LOCK WAS PREVIOUSLY ACHIEVED ...
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... Connect REFMON pin to REFSEL pin. Frequency Status Monitors The AD9518 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency. A diagram showing their location in the PLL is shown in Figure 39 ...
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... REFIN pins, and that the PLL be set up properly to lock the PLL loop. During the first initialization after a power- reset of the AD9518, a VCO calibration sequence is initiated by setting Register 0x018[0] = 1b. This can be done during initial setup, before executing an update registers operation (Register 0x232[0] = 1b) ...
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... To connect the LVPECL outputs directly to the internal VCO or CLK, the VCO divider must be selected as the source to the distribution section, even if no channel uses it. Rev Page Data Sheet AD9518 has two clock input sources: VCO Divider Used Not used Used ...
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... An odd division must be set When not bypassed or corrected by the DCC function, the duty cycle of each channel divider output is the numerical value 1)/( 2), expressed as a percentage (%). Rev Page AD9518-1 for Divider 0, Divider 1, and Divider 2 X Low Cycles High Cycles ...
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... AD9518-1 The duty cycle at the output of the channel divider for various configurations is shown in Table 33 to Table 35. Table 33. Duty Cycle with VCO Divider, Input Duty Cycle Is 50% D Output Duty Cycle VCO X Divider DCCOFF = 1 Even 1 (divider 50% bypassed) Odd = 3 1 (divider 33.3% bypassed) Odd = 5 ...
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... SYNC signal with respect to the clock edges inside the AD9518. The delay from the SYNC rising edge to the beginning of synchronized output clocking is between 14 and 15 cycles of clock at the channel ...
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... Chip Power-Down via PD The AD9518 pulling the PD pin low. Power-down turns off most of the functions and currents inside the AD9518. The chip remains in this power-down state until PD is brought back to logic high. When the into its registers prior to the power-down, unless the registers are changed by new programming while the PD pin is held low ...
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... Register 0x230[ (see the Distribution Power-Down section). Individual Circuit Block Power-Down Other AD9518 circuit blocks (such as CLK, REF1, and REF2) can be powered down individually. This gives flexibility in configuring the part for power savings whenever certain chip functions are not needed. Rev Page AD9518-1 ...
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... Communication Cycle—Instruction Plus Data There are two parts to a communication cycle with the AD9518. The first part writes a 16-bit instruction word into the AD9518, coincident with the first 16 SCLK rising edges. The instruction ...
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... Only Bits[A9:A0] are needed to cover the range of the 0x232 registers used by the AD9518. Bits[A12:A10] must always be set to 0b. For multibyte transfers, this address is the starting byte address. In MSB first mode, subsequent bytes decrement the address. ...
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... AD9518-1 Table 39. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 W1 W0 A12 = 0 R/W CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 46. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data ...
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... Minimum period that SCLK should logic high state HIGH t Minimum period that SCLK should logic low state LOW t SCLK to valid SDIO and SDO (see Figure 49 CLK t t HIGH LOW t DH BIT N BIT Figure 51. Serial Control Port Timing Diagram—Write Rev Page AD9518 ...
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... Junction-to-top-of-package characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-2 (still air) JT Ψ Junction-to-top-of-package characterization parameter, 2.0 m/sec airflow per JEDEC JESD51-2 (still air) JT Use the following equation to determine the junction temperature of the AD9518 on the application PCB (Ψ × PD) J ...
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... REF1 Differential power-on power-on reference Holdover External Holdover enable holdover enable control REF2 REF1 Digital frequency > frequency > lock detect threshold threshold AD9518-1 Default Value (Hex) 0x18 0x61 0x00 0x7D 0x01 0x00 0x00 0x03 0x00 0x06 0x00 0x06 0x00 0x00 0x00 0x00 ...
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... AD9518-1 Reg. Addr. (Hex) Parameter Bit 7 (MSB) Bit 6 LVPECL Outputs 0x0F0 OUT0 0x0F1 OUT1 0x0F2 OUT2 0x0F3 OUT3 0x0F4 OUT4 0x0F5 OUT5 0x0F6 to 0x13F 0x140 to 0x143 0x144 to 0x18F LVPECL Channel Dividers 0x190 Divider 0 (PECL) 0x191 Divider 0 Divider 0 bypass nosync 0x192 Blank ...
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... Selects unidirectional or bidirectional data transfer mode. 0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default). 1: SDO used for read, SDIO used for write; unidirectional mode. Uniquely identifies the dash version (-0 through -4) of the AD9518. AD9518-0: 0x21. AD9518-1: 0x61. ...
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... AD9518-1 Table 44. PLL Reg. Addr. (Hex) Bits Name Description 0x010 7 PFD polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires positive polarity; Bit 7 = 0b. 0: positive; higher control voltage produces higher frequency (default). ...
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... Status of VCO frequency; active low LVL Selected reference (low = REF2, high = REF1 LVL Digital lock detect (DLD); active low LVL Holdover active; active low LVL LD pin comparator output; active low. Rev Page AD9518-1 ...
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... AD9518-1 Reg. Addr. (Hex) Bits Name Description [1:0] Antibacklash pulse 1 width 0x018 [6:5] Lock detect counter Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked condition Digital lock detect If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital window lock detect flag is set ...
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... Status of VCO frequency; active low LVL Selected reference (low = REF2, high = REF1 LVL Digital lock detect (DLD); active low LVL Holdover active; active low LVL Not available. Do not use. Rev Page AD9518-1 ...
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... AD9518-1 Reg. Addr. (Hex) Bits Name Description 0x01B 7 VCO frequency Enables or disables VCO frequency monitor. monitor 0: disables VCO frequency monitor (default). 1: enables VCO frequency monitor. 6 REF2 (REFIN) Enables or disables REF2 frequency monitor. frequency monitor 0: disables REF2 frequency monitor (default). 1: enables REF2 frequency monitor. ...
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... VCO frequency is greater than the threshold. 2 REF2 frequency > Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by threshold Register 0x1A, Bit 6. 0: REF2 frequency is less than threshold frequency. 1: REF2 frequency is greater than threshold frequency. Rev Page AD9518-1 ...
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... AD9518-1 Reg. Addr. (Hex) Bits Name Description 1 REF1 frequency > Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency threshold set by Register 0x01A, Bit 6. 0: REF1 frequency is less than threshold frequency. 1: REF1 frequency is greater than threshold frequency. 0 Digital lock detect Read-only register ...
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... Normal operation. 1 Partial power-down, reference on; use only if there are no external load resistors. 0 Partial power-down, reference on, safe LVPECL power-down (default). 1 Total power-down, reference off; use only if there are no external load resistors. Rev Page AD9518-1 Output On Off Off Off Output On Off Off ...
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... AD9518-1 Table 46. LVPECL Channel Dividers Reg. Addr. (Hex) Bits Name 0x190 [7:4] Divider 0 low cycles [3:0] Divider 0 high cycles 0x191 7 Divider 0 bypass 6 Divider 0 nosync 5 Divider 0 force high 4 Divider 0 start high [3:0] Divider 0 phase offset 0x192 1 Divider 0 direct to output 0 Divider 0 DCCOFF 0x193 [7:4] Divider 1 low cycles ...
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... Output static. Note that setting the VCO divider static should occur only after VCO calibration Output static. Note that setting the VCO divider static should occur only after VCO calibration Output static. Note that setting the VCO divider static should occur only after VCO calibration. Rev Page AD9518-1 ...
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... AD9518-1 Reg. Addr (Hex) Bits Name 0x1E1 4 Power down clock input section 3 Power down VCO clock interface 2 Power down VCO and CLK 1 Select VCO or CLK 0 Bypass VCO divider Table 48. System Reg. Addr. (Hex) Bits Name 0x230 2 Power down SYNC 1 Power down distribution ...
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... APPLICATIONS INFORMATION FREQUENCY PLANNING USING THE AD9518 The AD9518 is a highly flexible PLL. When choosing the PLL settings and version of the AD9518, keep in mind the following guidelines. The AD9518 has the following four frequency dividers: the reference (or R) divider, the feedback (or N) divider, the VCO divider, and the channel divider ...
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... TRANSMISSION LINE 200Ω 200Ω = 2.5 V, the 50 Ω termination S_LVPECL of the LVPECL OL on the AD9518 should equal V S_LVPECL − the actual S_LVPECL − 1.3 V because there is S_LVPECL AD9518 LVPECL driver = 2.5 V, except that the pull- S_LVPECL V S LVPECL of S ...
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... Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Rev Page 0.30 0.23 0.18 PIN 1 INDICATOR 5.55 EXPOSED 5.50 SQ PAD 5.45 (BOTTOM VIEW 0.22 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-48-8 CP-48-8 AD9518-1 ...
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... AD9518-1 NOTES Rev Page Data Sheet ...
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... Data Sheet NOTES Rev Page AD9518-1 ...
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... AD9518-1 NOTES ©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06430-0-1/12(C) Rev Page Data Sheet ...