AD9518-1A-PCBZ AD [Analog Devices], AD9518-1A-PCBZ Datasheet - Page 4

• Manufacturer Part Number: AD9518-1A-PCBZ
• Description: 6-Output Clock Generator with Integrated 2.5 GHz VCO
• Manufacturer: AD [Analog Devices]

AD9518-1
SPECIFICATIONS
Typical values are given for V
Minimum and maximum values are given over full V
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
V
V
V
RSET Pin Resistor
CPRSET Pin Resistor
BYPASS Pin Capacitor
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
REFERENCE INPUTS
PHASE/FREQUENCY DETECTOR (PFD)
S
S_LVPECL
CP
Pulse Width High/Low
PFD Input Frequency
Antibacklash Pulse Width
Frequency Range
VCO Gain (K
Tuning Voltage (V
Frequency Pushing (Open-Loop)
Phase Noise at 100 kHz Offset
Phase Noise at 1 MHz Offset
Differential Mode (REFIN, REFIN)
Dual Single-Ended Mode (REF1, REF2)
Input Capacitance
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
VCO
)
T
)
S
= V
S_LVPECL
= 3.3 V ± 5%; V
Min
3.135
2.375
V
2.7
Min
2300
0.5
0
1.35
1.30
4.0
4.4
20
0
2.0
−100
1.8
S
Typ
3.3
4.12
5.1
220
Typ
50
1
−105
−124
250
1.60
1.50
4.8
5.3
0.8
2
1.3
2.9
6.0
S
and T
S
≤ V
A
Max
3.465
V
5.25
10
Max
2650
V
250
1.75
1.60
5.9
6.4
250
250
0.8
+100
100
45
CP
(−40°C to +85°C) variation.
S
− 0.5
Rev. C | Page 4 of 64
CP
≤ 5.25 V; T
Unit
V
V
V
kΩ
kΩ
nF
Unit
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
MHz
mV p-p
V
V
kΩ
kΩ
MHz
MHz
V p-p
V
V
µA
ns
pF
MHz
MHz
ns
ns
ns
A
= 25°C; R
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA);
actual current can be calculated by CP_lsb = 3.06/CPRSET;
connect to ground
Bypass for internal LDO regulator; necessary for LDO stability;
connect to ground
Test Conditions/Comments
See Figure 11
See Figure 6
V
spurs may increase due to CP up/down mismatch
f = 2475 MHz
f = 2475 MHz
Differential mode (can accommodate single-ended input by
ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled; be careful
to match V
PLL figure of merit (FOM) increases with increasing slew rate
(see Figure 10);
LVPECL and LVDS signals
Self-bias voltage of REFIN
Self-bias voltage of REFIN
Self-biased
Self-biased
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/µs
Slew rate > 50 V/µs; CMOS levels
Should not exceed V
This value determines the allowable input duty cycle and is the
amount of time that a square wave is high/low
Each pin, REFIN/REFIN (REF1/REF2)
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
Register 0x017[1:0] = 01b
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
Register 0x017[1:0] = 10b
CP
≤ V
S
SET
when using internal VCO; outside of this range, the CP
CM
= 4.12 kΩ; CP
1
1
(self-bias voltage)
the input sensitivity is sufficient for ac-coupled
S
p-p
1
RSET
1
= 5.1 kΩ, unless otherwise noted.
Data Sheet