AD9518-3A-PCBZ AD [Analog Devices], AD9518-3A-PCBZ Datasheet - Page 40

• Manufacturer Part Number: AD9518-3A-PCBZ
• Description: 6-Output Clock Generator with 6-Output Clock Generator with
• Manufacturer: AD [Analog Devices]

AD9518-3
SERIAL CONTROL PORT
The
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9518
transfer formats, including both the Motorola SPI and Intel®
SSR® protocols. The serial control port allows read/write access
to all registers that configure the AD9518. Single or multiple
byte transfers are supported, as well as MSB first or LSB first
transfer formats. The
configured for a single bidirectional I/O pin (SDIO only)
or for two unidirectional I/O pins (SDIO/SDO). By default,
the
instruction is the only instruction mode supported).
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and
writes. Write data bits are registered on the rising edge of this
clock, and read data bits are registered on the falling edge. This
pin is internally pulled down by a 30 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin that acts
as either an input only (unidirectional mode) or as both an
input and an output (bidirectional mode). The
to the bidirectional I/O mode (Register 0x000[0] = 0b).
SDO (serial data out) is used only in the unidirectional I/O mode
(Register 0x000[0] = 1b) as a separate output pin for reading
back data.
CS (chip select bar) is an active low control that gates the read
and write cycles. When CS is high, SDO and SDIO are in a high
impedance state. This pin is internally pulled up by a 30 kΩ
resistor to VS.
GENERAL OPERATION OF SERIAL CONTROL PORT
A write or a read operation to the
CS low.
CS stalled high is supported in modes where three or fewer bytes
of data (plus instruction data) are transferred (see
In these modes,
boundary, allowing time for the system controller to process the
next byte. CS can go high on byte boundaries only and can go
high during either part (instruction or data) of the transfer.
AD9518
AD9518
serial control port is compatible with most synchronous
is in bidirectional mode, long instruction (long
serial control port is a flexible, synchronous, serial
CS can temporarily return high on any byte
SCLK
Figure 44. Serial Control Port
SDIO
SDO
AD9518
CS
13
14
15
16
AD9518-3
serial control port can be
CONTROL
SERIAL
PORT
AD9518
is initiated by pulling
AD9518
Table 37
defaults
).
Rev. B | Page 40 of 64
During this period, the serial control port state machine enters
a wait state until all data is sent. If the system controller decides
to abort the transfer before all of the data is sent, the state machine
must be reset, either by completing the remaining transfers or
by returning CS low for at least one complete SCLK cycle (but
less than eight SCLK cycles). Raising CS on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 37), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented (see the MSB/LSB
First Transfers section). CS must be raised at the end of the last
byte to be transferred, thereby ending the stream mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9518.
The first part writes a 16-bit instruction word into the AD9518,
coincident with the first 16 SCLK rising edges. The instruction
word provides the
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
is the transfer of data into the serial control port buffer of the
AD9518. Data bits are registered on the rising edge of SCLK.
The length of the transfer (1, 2, 3 bytes or streaming mode) is
indicated by two bits ([W1:W0]) in the instruction byte. When
the transfer is 1, 2, or 3 bytes, but not streaming, CS can be raised
after each sequence of eight bits to stall the bus (except after the
last byte, where it ends the cycle). When the bus is stalled, the serial
transfer resumes when CS is lowered. Raising CS on a nonbyte
boundary resets the serial control port. During a write, streaming
mode does not skip over reserved or blank registers; therefore,
the user must know the bit pattern to write to the reserved registers
to preserve proper operation of the part. Refer to the control
register map (see
reserved registers is nonzero. It does not matter what data is
written to blank registers.
Because data is written into a serial control port buffer area, and
not directly into the actual control registers of the AD9518, an
additional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9518,
thereby causing them to become active. The update registers
operation consists of setting Register 0x232[0] = 1b (this bit is
self-clearing). Any number of bytes of data can be changed before
an update registers operation is executed. The update registers
operation simultaneously actuates all register changes that have
been written to the buffer since any previous update.
Table 42
AD9518
) to determine if the default value for
serial control port with information
Data Sheet