AD9518-3A-PCBZ AD [Analog Devices], AD9518-3A-PCBZ Datasheet - Page 49

• Manufacturer Part Number: AD9518-3A-PCBZ
• Description: 6-Output Clock Generator with 6-Output Clock Generator with
• Manufacturer: AD [Analog Devices]

Data Sheet
Reg.
Addr.
(Hex)
0x017
Bits
[2:0]
[7:2]
Name
Prescaler P
STATUS pin control
Description
Prescaler: DM = dual modulus and FD = fixed divide.
2
0
0
0
0
1
1
1
1
Selects the signal that is connected to the STATUS pin.
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
6
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
1
5
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Mode
FD
FD
DM
DM
DM
DM
DM
FD
4
0
0
0
0
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
3
0
0
1
1
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Prescaler
Divide-by-1.
Divide-by-2.
Divide-by-2 (2/3 mode).
Divide-by-4 (4/5 mode).
Divide-by-8 (8/9 mode).
Divide-by-16 (16/17 mode).
Divide-by-32 (32/33 mode) (default).
Divide-by-3.
2
0
1
0
1
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. B | Page 49 of 64
Level or
Dynamic
Signal
DYN
LVL
DYN
DYN
LVL
DYN
DYN
DYN
DYN
LVL
DYN
DYN
DYN
DYN
DYN
LVL
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Signal at STATUS Pin
Ground (dc) (default).
N divider output (after the delay).
R divider output (after the delay).
A divider output.
Prescaler output.
PFD up pulse.
PFD down pulse.
Ground (dc); for all other cases of 0XXXXXb not specified previously.
The selections that follow are the same as REFMON.
Ground (dc).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in differential mode).
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference); active high.
Status of unselected reference (not available in differential mode);
active high.
Status REF1 frequency; active high.
Status REF2 frequency; active high.
(Status REF1 frequency) AND (status REF2 frequency).
(DLD) AND (status of selected reference) AND (status of VCO).
Status of VCO frequency; active high.
Selected reference (low = REF1, high = REF2).
Digital lock detect (DLD); active high.
Holdover active; active high.
LD pin comparator output; active high.
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in differential mode).
Unselected reference to PLL (not available when in differential mode).
Status of selected reference (status of differential reference); active low.
Status of unselected reference (not available in differential mode); active low.
Status of REF1 frequency; active low.
Status of REF2 frequency; active low.
(Status of REF1 frequency) AND (status of REF2 frequency) .
(DLD) AND (status of selected reference) AND (status of VCO) .
Status of VCO frequency; active low.
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD); active low.
Holdover active; active low.
LD pin comparator output; active low.
AD9518-3