CY7C1471V33_12 CYPRESS [Cypress Semiconductor], CY7C1471V33_12 Datasheet
CY7C1471V33_12
Related parts for CY7C1471V33_12
CY7C1471V33_12 Summary of contents
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M × 36) Flow-Through SRAM with NoBL™ Architecture Features No Bus Latency™ (NoBL™) architecture eliminates dead ■ cycles between write and read cycles Supports up to 133 MHz bus operations with zero wait states ■ Data is transferred ...
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Logic Block Diagram – CY7C1471V33 ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN ADV/ CE1 CE2 CE3 ZZ Document Number: 38-05288 Rev A1 ...
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Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Single Read Accesses ................................................ 6 Burst Read Accesses .................................................. 6 Single Write Accesses ................................................. 6 Burst Write Accesses .................................................. 6 Sleep Mode ................................................................. 6 Interleaved Burst Address ...
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Pin Configurations DQP DDQ BYTE DDQ ...
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Pin Definitions Name I Input- Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK synchronous A are fed to the two-bit burst counter. [1:0] ...
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Functional Overview The CY7C1471V33 is synchronous flow through burst SRAMs designed specifically to eliminate wait states during write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with ...
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Interleaved Burst Address Table (MODE = Floating First Second Third Address Address Address A1:A0 A1:A0 A1: Mode Electrical Characteristics Parameter Description I Sleep ...
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Truth Table The truth table for CY7C1471V33 follows. Operation Deselect cycle Deselect cycle Deselect cycle Continue deselect cycle Read cycle (begin burst) Read cycle (continue burst) NOP/dummy read (begin burst) Dummy read (continue burst) Write cycle (begin burst) Write cycle ...
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Truth Table for Read/Write The read-write truth table for CY7C1471V33 follows. Function Read Write no bytes written Write byte A – (DQ and DQP ) A A Write byte B – (DQ and DQP ) B B Write byte C ...
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Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied .......................................... –55 C to +125 C Supply voltage ...
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Capacitance [13] Parameter Description C Address input capacitance ADDRESS C Data input capacitance DATA C Control input capacitance CTRL C Clock input capacitance CLK C Input/Output capacitance IO Thermal Resistance [13] Parameter Description Thermal resistance JA (junction to ambient) ...
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Switching Characteristics Over the Operating Range [14, 15] Parameter [16] t POWER Clock t Clock cycle time CYC t Clock HIGH CH t Clock LOW CL Output Times t Data output valid after CLK rise CDV t Data output hold ...
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Switching Waveforms CYC CLK t CENS t CENH t CH CEN t CES t CEH CE ADV/ ADDRESS D(A1 COM M ...
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Switching Waveforms (continued) Figure 4. NOP, STALL and DESELECT Cycles 1 2 CLK CEN CE ADV/ [A: ADDRESS D(A1) DQ COMMAND WRITE READ D(A1) Q(A2) Notes 23. For this waveform ZZ is tied LOW. 24. When ...
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Switching Waveforms (continued) CLK ZZ I SUPPLY ALL INPUTS (except ZZ) Outputs (Q) Notes 26. Device must be deselected when entering ZZ mode. See 27. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05288 Rev. *N ...
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Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress ...
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Package Diagrams Figure 6. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 Document Number: 38-05288 Rev. *N CY7C1471V33 51-85050 *D Page ...
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Acronyms Acronym Description CMOS complementary metal oxide semiconductor CE chip enable CEN clock enable I/O input/output JEDEC joint electron devices engineering council NoBL no bus latency OE output enable SRAM static random access memory TQFP thin quad flat pack TTL ...
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Document History Page Document Title: CY7C1471V33, 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05288 Orig. of Rev. ECN Change ** 114675 PKS *A 121521 CJM *B 223721 NJY *C 235012 RYQ *D 243572 NJY *E ...
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Document History Page (continued) Document Title: CY7C1471V33, 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05288 Orig. of Rev. ECN Change *G 331513 PCI *H 416221 RXU *I 472335 VKN *J 1274732 VKN / AESA *K ...
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Document History Page (continued) Document Title: CY7C1471V33, 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05288 Orig. of Rev. ECN Change *N 3633894 PRIT Document Number: 38-05288 Rev. *N Submission Date 06/01/2012 Updated Features (Removed CY7C1473V33, ...
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