CY7C1480V33_11 CYPRESS [Cypress Semiconductor], CY7C1480V33_11 Datasheet

CY7C1480V33_11

Manufacturer Part Number

CY7C1480V33_11

Description

72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7C1480V33_11.pdf (36 pages)

Current page: 1 of 36
Download datasheet (2Mb)

72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM

Features

■

Selection Guide

Note

Cypress Semiconductor Corporation

Document Number: 38-05283 Rev. *K

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

1. For best practices recommendations, please refer to the Cypress application note

Supports bus operation up to 250 MHz

Available speed grades are 250, 200, and 167 MHz

Registered inputs and outputs for pipelined operation

3.3V core power supply

2.5V/3.3V I/O operation

Fast clock-to-output times

❐

Provide high performance 3-1-1-1 access rate

User selectable burst counter supporting Intel

Pentium

Separate processor and controller address strobes

Synchronous self timed writes

Asynchronous output enable

Single cycle chip deselect

CY7C1480V33, CY7C1482V33 available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA

package. CY7C1486V33 available in Pb-free and non-Pb-free

209-ball FBGA package

IEEE 1149.1 JTAG-Compatible Boundary Scan

“ZZ” Sleep Mode option

3.0 ns (for 250 MHz device)

interleaved or linear burst sequences

•

198 Champion Court

72-Mbit (2 M × 36/4 M × 18/1 M × 72)

250 MHz

AN1064, SRAM System

Functional Description

The

integrates 2 M × 36/4 M × 18/1 M × 72 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE

Chip Enables (CE

ADSP, and ADV), Write Enables (BW

Write (GW). Asynchronous inputs include the Output Enable

(OE) and the ZZ pin.

Addresses and chip enables are registered at the rising edge of

the clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see

page 11

bytes wide as controlled by the byte write control inputs. GW

when active LOW causes all bytes to be written.

The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates

from a +3.3 V core power supply while all outputs may operate

with either a +2.5 or +3.3 V supply. All inputs and outputs are

JEDEC standard JESD8-5 compatible.

500

120

3.0

•

CY7C1480V33/CY7C1482V33/CY7C1486V33

for further details). Write cycles can be one to two or four

San Jose

200 MHz

Pin Definitions on page 8

500

120

Pipelined Sync SRAM

3.0

Guidelines.

and CE

CA 95134-1709

), Burst Control inputs (ADSC,

167 MHz

[1]

450

120

3.4

CY7C1480V33

CY7C1482V33

CY7C1486V33

, and BWE), and Global

Revised May 14, 2011

•

and

), depth-expansion

Truth Table on

408-943-2600

Unit

SRAM

[+] Feedback

Related parts for CY7C1480V33_11

Related keywords

CY7C1480V33_11 datasheet
CY7C1480V33_11 data sheet
CY7C1480V33_11 pdf datasheet
CY7C1480V33_11 component
CY7C1480V33_11 part
CY7C1480V33_11 distributor
CY7C1480V33_11 RoHS
CY7C1480V33_11 datasheet download