CAT28C256 CATALYST [Catalyst Semiconductor], CAT28C256 Datasheet

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CAT28C256

Manufacturer Part Number
CAT28C256
Description
32K-Bit Parallel E2PROM
Manufacturer
CATALYST [Catalyst Semiconductor]
Datasheet

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CAT28C256
32K-Bit Parallel E
FEATURES
DESCRIPTION
The CAT28C256 is a fast, low power, 5V-only CMOS
parallel E
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and V
additional timing and protection hardware. DATA Polling
and Toggle status bits signal the start and end of the self-
timed write cycle. Additionally, the CAT28C256 features
hardware and software write protection.
BLOCK DIAGRAM
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Fast Read Access Times: 120/150ns
Low Power CMOS Dissipation:
–Active: 25 mA Max.
–Standby: 150 A Max.
Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
Fast Write Cycle Time:
–5ms Max
CMOS and TTL Compatible I/O
A 6 –A 14
A 0 –A 5
V CC
2
WE
CE
OE
PROM organized as 32K x 8-bits. It requires a
CC
power up/down write protection eliminate
2
PROM
ADDR. BUFFER
ADDR. BUFFER
INADVERTENT
PROTECTION
TIMER
& LATCHES
CONTROL
& LATCHES
LOGIC
WRITE
1
DATA POLLING
HIGH VOLTAGE
TOGGLE BIT
GENERATOR
The CAT28C256 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
DECODER
COLUMN
DECODER
AND
Hardware and Software Write Protection
Automatic Page Write Operation:
–1 to 64 Bytes in 5ms
–Page Load Timer
End of Write Detection:
–Toggle Bit
–DATA Polling
100,000 Program/Erase Cycles
100 Year Data Retention
Commerical, Industrial and Automotive
Temperature Ranges
ROW
I/O BUFFERS
32,768 x 8
I/O 0 –I/O 7
E
ARRAY
2
PROM
64 BYTE PAGE
REGISTER
Doc. No. 25020-0A 2/98
5096 FHD F02

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CAT28C256 Summary of contents

Page 1

... Write Cycle with Auto-Clear Fast Write Cycle Time: –5ms Max CMOS and TTL Compatible I/O DESCRIPTION The CAT28C256 is a fast, low power, 5V-only CMOS 2 parallel E PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto- ...

Page 2

DIP Package ( I I I/O ...

Page 3

... V +0.3 CC –0.3 0.8 2.4 0.4 3.5 +2.0V for periods of less than 20 ns CAT28C256 Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Units Test Conditions f=8MH IL z All I/O’s Open f=8MH ...

Page 4

MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit CAPACITANCE 1.0 MHz Symbol Test (1) C Input/Output Capacitance I/O (1) C ...

Page 5

... V REFERENCE POINTS 0.8 V 1.3V 1N914 3.3K DEVICE UNDER TEST 100 INCLUDES JIG CAPACITANCE max. stops the timer. BLC 5 CAT28C256 Max. Units 100 s 5096 FHD F03 OUT 5096 FHD F04 Doc. No. 25020-0A 2/98 ...

Page 6

... CAT28C256 DEVICE OPERATION Read Data stored in the CAT28C256 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment ...

Page 7

... Page Write The page write mode of the CAT28C256 (essentially an extended BYTE WRITE mode) allows from bytes of data to be programmed within a single E cycle. This effectively reduces the byte-write time by a factor of 64. Following an initial WRITE operation (WE pulsed low, for t , and then high) the page write mode can begin by ...

Page 8

... Beginning and ending state of I/O is indeterminate. 6 Doc. No. 25020-0A 2/98 Toggle Bit In addition to the DATA Polling feature of the CAT28C256, the device offers an additional method for determining the completion of a write cycle. While a write cycle is in (I/O –I/O progress, reading data from the device will result in I/O ...

Page 9

... INIT algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28C256 is in the standard operating mode). Figure 10. Write Sequence for Deactivating (12) ...

Page 10

... 100,000 Cycle * -40˚C to +125˚C is available upon request Notes: (1) The device used in the above example is a CAT28C256HNI-15T (100,000 Cycle Endurance, PLCC, Industrial temperature, 150ns Access Time, Tape & Reel). Doc. No. 25020-0A 2/98 To allow the user the ability to program the device with 2 ...

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