CAT28C64B CATALYST [Catalyst Semiconductor], CAT28C64B Datasheet - Page 10

• Manufacturer Part Number: CAT28C64B
• Description: 64K-Bit CMOS PARALLEL E2PROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

HARDWARE DATA PROTECTION
The following is a list of hardware data protection fea-
tures that are incorporated into the CAT28C64B.
(1) V
(2) A power on delay mechanism, t
(3) Write inhibit is activated by holding any one of OE
Figure 9. Write Sequence for Activating Software
Data Protection
Note:
(1)
Doc. No. 25006-0A 2/98 P-1
falls below 3.5V min.
teristics), provides a 5 to 10 ms delay before a write
sequence, after V
low, CE high or WE high.
Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
CC
sense provides for write protection when V
WRITE DATA:
WRITE DATA:
WRITE DATA:
PROTECTION ACTIVATED
WRITE DATA:
ADDRESS:
ADDRESS:
ADDRESS:
WRITE LAST BYTE
TO ANY ADDRESS
SOFTWARE DATA
LAST ADDRESS
CC
TO
has reached 3.5V min.
AA
1555
55
0AAA
A0
1555
XX
INIT
(1)
(see AC charac-
28C64B F12
CC
10
(4) Noise pulses of less than 20 ns on the WE or CE
SOFTWARE DATA PROTECTION
The CAT28C64B features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28C64B is
in the standard operating mode).
Figure 10. Write Sequence for Deactivating
Software Data Protection
inputs will not result in a write cycle.
WRITE DATA:
WRITE DATA:
WRITE DATA:
WRITE DATA:
WRITE DATA:
WRITE DATA:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
AA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
5094 FHD F09
BLC