CY7C1518AV18-278BZI CYPRESS [Cypress Semiconductor], CY7C1518AV18-278BZI Datasheet - Page 25

• Manufacturer Part Number: CY7C1518AV18-278BZI
• Description: 72-Mbit DDR-II SRAM 2-Word Burst Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Notes
Document Number: 001-06982 Rev. *C
26. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
27. Outputs are disabled (High-Z) one clock cycle after a NOP.
28. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
DQ
R/W
CQ
CQ#
LD
C#
C
K
K
A
NOP
t KHCH
1
t KH
t
t KL
t
SA
SC
A0
READ
2
t HC
t HA
t KHCH
t CYC
A1
t CQOH
READ
3
t CLZ
t KHKH
t CO
Figure 3. Read/Write/Deselect Sequence
Q00
NOP
4
t CCQO
t CQDOH
t DOH
Q01
t CQD
Q10
NOP
5
Q11
t CQOH
A2
t CHZ
WRITE
6
t KH
t SD
t HD
CY7C1516AV18, CY7C1527AV18
CY7C1518AV18, CY7C1520AV18
t CCQO
t KL
D20
A3
WRITE
7
[26, 27, 28]
D21
t CQH
t CYC
t SD
D30
A4
READ
8
t HD
DON’T CARE
t KHKH
D31
t CQHCQH
9
UNDEFINED
Q40
Page 25 of 30
10
Q41
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