CAT28LV64 CATALYST [Catalyst Semiconductor], CAT28LV64 Datasheet - Page 9

• Manufacturer Part Number: CAT28LV64
• Description: 64K-Bit CMOS PARALLEL E2PROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

Note:
(1)
HARDWARE DATA PROTECTION
The following is a list of hardware data protection fea-
tures that are incorporated into the CAT28LV64.
(1) V
(2) A power on delay mechanism, t
(3) Write inhibit is activated by holding any one of OE
Figure 9. Write Sequence for Activating Software
falls below 2.0V min.
teristics), provides a 5 to 10 ms delay before a write
sequence, after V
low, CE high or WE high.
Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
CC
sense provides for write protection when V
Data Protection
WRITE DATA:
WRITE DATA:
WRITE DATA:
PROTECTION ACTIVATED
WRITE DATA:
ADDRESS:
ADDRESS:
ADDRESS:
WRITE LAST BYTE
TO ANY ADDRESS
SOFTWARE DATA
LAST ADDRESS
CC
has reached 2.40V min.
TO
AA
1555
55
0AAA
A0
1555
XX
INIT
(1)
(see AC charac-
28LV64 F12
CC
9
(4) Noise pulses of less than 20 ns on the WE or CE
SOFTWARE DATA PROTECTION
The CAT28LV64 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28LV64 is
in the standard operating mode).
Figure 10. Write Sequence for Deactivating
inputs will not result in a write cycle.
Software Data Protection
WRITE DATA:
WRITE DATA:
WRITE DATA:
WRITE DATA:
WRITE DATA:
WRITE DATA:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
AA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
Doc. No. 25035-00 2/98
5094 FHD F09
BLC