ADF4351BCPZ AD [Analog Devices], ADF4351BCPZ Datasheet - Page 19

• Manufacturer Part Number: ADF4351BCPZ
• Description: Wideband Synthesizer
• Manufacturer: AD [Analog Devices]

Data Sheet
Reference Doubler
Setting the DB25 bit to 0 disables the doubler and feeds the REF
signal directly into the 10-bit R counter. Setting this bit to 1 multi-
plies the REF
the 10-bit R counter. When the doubler is disabled, the REF
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of REF
When the doubler is enabled and the low spur mode is selected,
the in-band phase noise performance is sensitive to the REF
cycle. The phase noise degradation can be as much as 5 dB for
REF
is insensitive to the REF
when the doubler is disabled.
The maximum allowable REF
enabled is 30 MHz.
RDIV2
Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop
between the R counter and the PFD, which extends the maximum
REF
appear at the PFD input, which is necessary for cycle slip reduction.
10-Bit R Counter
The 10-bit R counter (Bits[DB23:DB14]) allows the input reference
frequency (REF
clock to the PFD. Division ratios from 1 to 1023 are allowed.
Double Buffer
The DB13 bit enables or disables double buffering of
Bits[DB22:DB20] in Register 4. For information about how
double buffering works, see the Program Modes section.
Charge Pump Current Setting
Bits[DB12:DB9] set the charge pump current. This value should
be set to the charge pump current that the loop filter is designed
with (see Figure 26).
Lock Detect Function (LDF)
The DB8 bit configures the lock detect function (LDF). The LDF
controls the number of PFD cycles monitored by the lock detect
circuit to ascertain whether lock has been achieved. When DB8 is
set to 0, the number of PFD cycles monitored is 40. When DB8
is set to 1, the number of PFD cycles monitored is 5. It is recom-
mended that the DB8 bit be set to 0 for fractional-N mode and
to 1 for integer-N mode.
Lock Detect Precision (LDP)
The lock detect precision bit (Bit DB7) sets the comparison
window in the lock detect circuit. When DB7 is set to 0, the
comparison window is 10 ns; when DB7 is set to 1, the window
is 6 ns. The lock detect circuit goes high when n consecutive
PFD cycles are less than the comparison window value; n is set
by the LDF bit (DB8). For example, with DB8 = 0 and DB7 = 0,
40 consecutive PFD cycles of 10 ns or less must occur before
digital lock detect goes high.
IN
IN
duty cycles outside a 45% to 55% range. The phase noise
input rate. This function allows a 50% duty cycle signal to
IN
frequency by a factor of 2 before feeding it into
IN
) to be divided down to produce the reference
IN
become active edges at the PFD input.
IN
duty cycle in the low noise mode and
IN
frequency when the doubler is
IN
duty
IN
Rev. 0 | Page 19 of 28
IN
For fractional-N applications, the recommended setting for
Bits[DB8:DB7] is 00; for integer-N applications, the recom-
mended setting for Bits[DB8:DB7] is 11.
Phase Detector Polarity
The DB6 bit sets the phase detector polarity. When a passive
loop filter or a noninverting active loop filter is used, this bit
should be set to 1. If an active filter with an inverting charac-
teristic is used, this bit should be set to 0.
Power-Down (PD)
The DB5 bit provides the programmable power-down mode.
Setting this bit to 1 performs a power-down. Setting this bit to 0
returns the synthesizer to normal operation. In software power-
down mode, the part retains all information in its registers. The
register contents are lost only if the supply voltages are removed.
When power-down is activated, the following events occur:
•
•
•
•
•
•
Charge Pump Three-State
Setting the DB4 bit to 1 puts the charge pump into three-state
mode. This bit should be set to 0 for normal operation.
Counter Reset
The DB3 bit is the reset bit for the R counter and the N counter
of the ADF4351. When this bit is set to 1, the RF synthesizer
N counter and R counter are held in reset. For normal opera-
tion, this bit should be set to 0.
REGISTER 3
Control Bits
When Bits[C3:C1] are set to 011, Register 3 is programmed.
Figure 27 shows the input data format for programming this
register.
Band Select Clock Mode
Setting the DB23 bit to 1 selects a faster logic sequence of band
selection, which is suitable for high PFD frequencies and is
necessary for fast lock applications. Setting the DB23 bit to 0 is
recommended for low PFD (<125 kHz) values. For the faster
band select logic modes (DB23 set to 1), the value of the band
select clock divider must be less than or equal to 254.
Antibacklash Pulse Width (ABP)
Bit DB22 sets the PFD antibacklash pulse width. When Bit DB22
is set to 0, the PFD antibacklash pulse width is 6 ns. This setting is
recommended for fractional-N use. When Bit DB22 is set to 1,
the PFD antibacklash pulse width is 3 ns, which results in phase
noise and spur improvements in integer-N operation. For
fractional-N operation, the 3 ns setting is not recommended.
Synthesizer counters are forced to their load state conditions.
VCO is powered down.
Charge pump is forced into three-state mode.
Digital lock detect circuitry is reset.
RF
Input registers remain active and capable of loading and
latching data.
OUT
buffers are disabled.
ADF4351