CAT5409WI-00 CATALYST [Catalyst Semiconductor], CAT5409WI-00 Datasheet - Page 5
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CAT5409WI-00
Manufacturer Part Number
CAT5409WI-00
Description
Manufacturer
CATALYST [Catalyst Semiconductor]
Datasheet
1.CAT5409WI-00.pdf
(16 pages)
WRITE CYCLE LIMITS
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Figure 1. Bus Timing
Figure 2. Write Cycle Timing
Figure 3. Start/Stop Timing
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Symbol
Symbol
N
T
V
I
LTH
DR
ZAP
END
t
PUR
(1)
(1) (2)
WR
(1)
(1)
SDA OUT
and t
SDA IN
SCL
SDA
SCL
PUW
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Parameter
Write Cycle Time
are delays required from the time V
t SU:STA
SDA
SCL
t F
8TH BIT
BYTE n
START CONDITION
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
t HD:STA
t LOW
ACK
t AA
CC
t HD:DAT
is stable until the specified operation can be initiated.
t HIGH
STOP
CONDITION
t LOW
5
t DH
t SU:DAT
t R
t WR
STOP CONDITION
START
CONDITION
1,000,000
2000
Min
100
100
t SU:STO
t BUF
Max
ADDRESS
Max
5
Doc. No. MD-2010 Rev. K
Cycles/Byte
CAT5409
Years
Units
mA
Units
V
ms